IEEE DASC VHDL PLI Task Force

The group was formed in at the Design Automation Conference in June 1997. It was initiated by a few companies of VHDL tools developers and users.

Mission and scope

Mission: Design of a standard Procedural Interface for VHDL.

• Design a standard procedural interface for VHDL. The outcome should be a specification that is implementor independent and which can be used on any VHDL compliant tool.
• Supports the current standard version of VHDL and any past versions as needed.
• The interface should define the semantics for a mixed language design and define the elaboration/instantiation and access methodology during runtime of foreign models.
• The interface will provide a mechanism to interact, control and communicate with a VHDL compliant tool.

The charter is to evaluate all options for post-elaboration and simulation runtime control and either choose an initial solution, merge existing ones or design a new one.

Technical commitee

Activities and achievements

VHDL PLI Requirements

Design guidelines

Meeting minutes

Schedule and documents

Schedule

Specifications and Papers

Contact Information

Requirements

There are 10 requirements.

The procedural interface functionality can be divided in 2 parts: the core functions and the utility functions.

core: The interface should provide core functionality that enables the development of applications such as:

• design traversals, netlisters,
• connectivity extractors,
• co-simulation, backplane interfaces,
• behavioral models,
• debugging environments,
• simulation testbench and verification,
• VHDL code profilers and coverage tools,
• VHDL decompilers,
• delay calculators.

These various types of applications require different capabilities to be supported by the VHDL procedural interface; they can be classified in 4 categories:

1. access to static HDL design data
2. access and modification of specific VHDL objects
3. simulation interaction and control
4. foreign model instantiation and intercommunication mechanism with VHDL design

Class 1 functionality should provide access to the elaborated model. Complete (with the exception of protected data see requirement # 2) behavioral and structural access is highly desirable for back end tools such as synthesis tools, delay calculators design verification tools. If the procedural interface provides complete access to the static design data it should be possible to decompile a design that was analyzed and regenerate an equivalent VHDL description. Delay calculation and back annotation through PLI is considered as very low priority. There are several reasons behind this decision:

1. No existing C interface has this capability,
2. SDF back annotation or proprietary delay calculation or back annotation tools have been used
for VHDL designs.
3. A group under the DASC is working on a new standard for delay calculation and annotation (DPC) and will fullfill this need. http://www.vhdl.org/dpcbecause some other methodologies

Class 3 functionality should provide the ability to change values of VHDL objects during elaboration or simulation. Valid objects that can be modified will be specified.

Class 3 functionality should provide simulation interaction such as the ability to schedule events and transactions, query the simulation state and time queue and interrupt the simulation engine at defined times or for various reasons.

Class 4 functionality should provide a mechanism to elaborate foreign models with VHDL models. This mechanism should specify how one can use a foreign model in a VHDL model and how the foreign model should access and propagate values to and from the VHDL model.

The interface should provide support for event-driven as well as for alternative algorithms for simulation.

Utilities: Core utility functions such as printing, displaying and comparison functions are necessary. The interface should provide an error handling mechanism, strong error detection and a set of known error codes that the user can reference. All of the PLI functions should give an indication of how and why they fail if they fail.

The access to protected models should be restricted to the information that can be found in a model vendor library and what is necessary for interfacing the library cells in the VHDL design.

The procedural interface sould provide functionality to allow the application to manage the lifetime of the memory allocated by the PLI.

The application cannot make assumptions about the underlaying data implementation. It must use the defined mechanisms for data manipulation.

The PLI should be ANSI C compatible.

The PLI should support simultaneous use and parallel read-only access to the same data. Note:Parallel modification (write access) to the same data may be indeterministic and may be implementation dependant. The design solution may determine the outcome of this issue.

The mechanism that the PLI interface provides for integrating PLI applications or models should be easily portable to major platforms, i.e. UNIX or NT.

The working group will evaluate if the PLI interface should require VITAL specific information.

The PLI should support a mechanism to save and restore PLI application state; after a restore operation, the VHDL compliant tool should be able to continue.

For simulation tools, the PLI should provide a mechanism to reset to time 0 which is the time just after simulation initialization.

TBD

Design guidelines

There are 7 guidelines.

#1 Do not preclude mixed signal VHDL.

#2 Provide for smooth crossing of VHDL/Verilog domains

#3 performance - The interface should provide fast access to data. In particular, when the interface functions are used for communicating with a simulator, where speed is the most important thing.

#4 capacity - The procedural interface should be able to handle large designs and should manage memory internally.

#5 versioning - A mechanism should be provided to determine adequate version information for the PLI interface, the simulator and relevant models.

#6 Function, data type names should be intuitive and seem natural to somebody who knows VHDL.

#7 The working group will evaluate relevant existing interfaces with the possibility of leveraging prior work.

Meeting minutes

There is no more meetings scheduled as the draft specification is completed.

Schedule

Specifications, papers

Presentation slides

VHDL PLI landing the PI zoo (powerpoint compressed file)

Papers

IVC/VIUF 1998: VHPI a VHDL Procedural interface and its applications frame 5 format)

VHDL PLI specification document

Outline

information model requirements

VHDL PLI standard draft (pdf format)

VHPI header file

VHPI class diagrams (jpeg format)

VHPI UML web browser

Issue Reports

We are using issue resolution reports to gather analysis and specifications of PLI functionality. The goal is to use these documents as the main basis for the PLI specification standard draft. They serve for recording analysis and decisions and will be used for broader external distribution and ballot. These reports contain cross-references to the VHDL'93 LRM 1076 .

The current effort is centralized on the specification of simulation control, value access and modification through PLI. This includes: updating values, scheduling transactions, accessing values and registering callbacks. The task force is concentrating on this very important part of PLI interface because it is the fundation for building PLI C models. Other parts of the PLI such as complete access to the elaborated model will come in another phase of our work. Below is the list of IRS we are working on and their status: TBC (to be created), Open, Pending, Complete, Approved.

Classification: Simulation modifications of values

Classification: Traversal and access

Classification: Simulation control with callbacks

Contact information

To subscribe to the email reflector send mail to: vhdlpli@vhdl.org

To become a member of the VHDL PLI Technical Committee send mail to: Francoise Martinolle Technical Committee Chair

About the vhdl.org machine

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