---------------------------------------------------------------------------- VHDL PLI IR number: 001 Classification: Simulation modification of values VHDL PLI version: 0.1 Title: Immediate update of signal values Summary: Allow PLI to immediately change the value of a signal or driver during a simulation cycle ------------------------------------------------------------------------------ Current Status: Open, pending or close PLI functions afftected: < fill up when PLI public function name is chosen > Related IRS: < list of related numbers > Key Words: simulation cycle, signal, driver Related LRM sections: Related VHDL PLI sections: < when the draft exists > Date Submitted: Requestor Priority: Assigned Priority: Author of Submission: Author's Affiliation: Author's Phone Number: Author's Net Address: Date Assigned: Description of Problem ---------------------- Example: PLI should provide the ability to modify a signal value in the current simulation cycle. Describe the different issues associated with this functionality that need to be addressed such as (in the above example) - access to a signal from anywhere in the design - value strength (normal, force, freeze) - scheduling transactions for drivers. - etc... Rationale --------- What are the user problems that we are trying to address. User requirements, type of applications... For example: - debugging capabilities, - co-simulation requirements - etc... Analysis -------------------- gather all relevant discussion, alternatives... Provide it as complete as possible, avoid redundancies, provide all argumentation... This is to ensure that second level of technical participant can understand the whole problem and vote accordingly. Proposed Solution ------------------ Describe the chosen solution. It could be design or even implementation details such as type definitions, function prototypes etc...Illustrate with examples if necessary. Recommendation for Future Revisions of Standard ----------------------------------------------- Things that were left over, options to consider in the next version... Special handling or differences with VHDL'87: ---------------------------------------------- List any differences with previous versions of the standard, backward incompatibility... special VHDL'87 behaviour.