-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- VHDL PLI SPECIFICATION OVERVIEW Official contact information, list of committee & participants, etc. history Table of Contents Preface - define mission/scope of VHDL PLI effort I Overview - a high-level description of VHDL PLI: o Philosophy of the interface (object-oriented design, VPI-like, ...) o ANSI C compatible interface o Provides access to post-elaboration model and runtime simulation data o Provides simulation interaction capabilities o Provides PLI model save/restore mechanism o Provides reset-to-time-zero mechanism for VHDL simulation tools o Multiple PLI models or applications may exist simultaneously in a design o User may create foreign architectures, subprograms (and processes?) o Autonomous PLI application registration II PLI Functional Interface 1. Quick overview of the different classes of functions 2. Handles - What is a handle - Handle management: allocation, deallocation, comparison 3. Information access functions [All sections will have: cross-references to the information model and PLI Reference sections, descriptive examples complete description of the capability provided] - Single relationship traversal functions (by class type or by name) - Iteration functions - Simple property access functions - Object value access function(s) - Object value assignment function(s) . immediate value updates (signals, variables...) . Transaction scheduling function(s) (pli_create_driver, pli_schedule_value...) 4. Callbacks - Functions for registering, removing, disabling, and enabling a callback - The various callback reasons, their descriptions and specific settings 5. Utility routines (e.g., access current simulation time, print an error message, write to a file, exit the simulation, get information about the foreign models or applications... ) III Information model - defines the subset of the full VHDL language that is accessible to users of the PLI, and their interrelations 1. Explanation of the information model formal specification (either graphic or textual, or both) 2. Static elaborated model - Design unit and Instance hierarchy - Declarations (objects, types) - Statements (concurrent, sequential) - Connectivity (sources, drivers, access to port map and generic map) - Foreign models, subprogram or IP access (parameters interface access and value, set subprogram return value) 3 Runtime simulation model - Callbacks - Kernel access (next event time queue...) IV VHDL PLI integration 1. Types of foreign models: architecture, subprogram, (process?) applications 2. VHDL source modifications & analysis [Foreign architecture, subprograms (processes?) specification format, including use of VHDL foreign attribute(s)] 3. Bootstrap: registration V. VHDL PLI execution [Describe restrictions on which PLI functions are available during which phases and what is happening at each phase] 1. Bootstrap phase 2. Elaboration phase 3. Initialization phase (describe the initial values of PLI foreign parameters or PLI objects, if any) 4. Simulation phase 5. Termination , exiting 6. Save/restart/reset phase 7. Callbacks, exceptions VI. Procedural Language Interface Reference alphabetical order of the PLI functions [All PLI functions above will have the following described: - C function signature (name, argument(s), return type) - Textual description of the function, including a short example - List of all possible error values returned, if applicable - Restrictions on usage (e.g., when can immediate signal value update call(s) be made) ] - cross-references to the PLI functional interface sections or info model ANNEX 1: Class textual description of the information model with explanation of the formal textual description ANNEX 2: PLI Standard include files and VHDL PLI standard package? Glossary - definition of frequently used acronyms and terms Potentially non-portable PLI calls Related standard documents & references Index Also needed, but perhaps as a separate appendix or document: o Examples demonstrating the use of the PLI interface