FYI:
-- Oz Levia Vice President, Engineering 408 567 1860 x201 Improv Systems, Inc. 408 567 1320(f) 2901 Tasman Dr., #112 ozl@improvsys.com Santa Clara, CA 95054 http://www.improvsys.com
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Received: from mail02.rapidsite.net by alterdial.UU.NET with ESMTP (peer crosschecked as: mail02.rapidsite.net [207.158.192.68]) id QQdual23824; Mon, 15 Dec 1997 07:52:57 -0500 (EST) Received: by mail02.rapidsite.net (8.8.5/8.8.5) id HAA21596 for mail53462@pop.net; Mon, 15 Dec 1997 07:52:57 -0500 (EST) Received: from rap11.cefriel.it by mail02.rapidsite.net (8.8.5/8.8.5) with ESMTP id HAA21530 for <ozl@improvsys.com>; Mon, 15 Dec 1997 07:52:54 -0500 (EST) Received: from rock.cefriel.it (rock.cefriel.it [131.175.5.131]) by rap11.cefriel.it (8.8.5/8.8.5) with ESMTP id NAA13399 for <sig-vhdl@rap.cefriel.it>; Mon, 15 Dec 1997 13:38:55 +0100 (MET) Received: by rock.cefriel.it with Internet Mail Service (5.5.1960.3) id <YQCF2KPM>; Mon, 15 Dec 1997 13:37:42 +0100 Received: from morgana.elet.polimi.it ([131.175.21.1]) by rock.cefriel.it with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.1960.3) id YQCF2KPL; Mon, 15 Dec 1997 13:37:33 +0100 Received: from pc-sci.elet.polimi.it by morgana.elet.polimi.it (5.65v3.2/1.1.10.5/07Jul97-0416PM) id AA30143; Mon, 15 Dec 1997 13:36:50 +0100 Message-Id: <3.0.32.19971215133610.006c7268@ipmel2> X-Sender: sciuto@ipmel2 X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Mon, 15 Dec 1997 13:36:10 +0100 To: sig-vhdl@cefriel.it From: Donatella Sciuto <sciuto@elet.polimi.it> Subject: FDL'98 Call Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Loop: detect
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D >CALL FOR CONTRIBUTIONS > >Forum on Design Languages (FDL'98) > >September 6 - 11, 1998 >Swiss Federal Institute of Technology, Lausanne, Switzerland > >featuring: > VHDL User's Forum in Europe (Sept. 7-8) > Workshop on Virtual Component Modeling (Sept. 8-9) > Workshop on System-Level Design Language (Sept. 10-11) > >A SIG-VHDL Event Sponsored by ECSI, Philips, Microswiss, >in cooperation with IFIP 10.5 >(Sponsor approval from IEEE Electron Devices Society, IEEE DATC, >and VHDL International pending) > >Web site: http://www.ireste.fr/fdl >=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D > >IMPORTANT DATES > > Contributions due: March 20, 1998 > Notification of acceptance: June 1, 1998 > Final contributions due: July 1, 1998 > Half-day tutorials: Sept. 6, 1998 > >The Forum on Design Languages (FDL) is a new forum to exchange = experiences >and to learn on new efforts and trends in the application of languages = and >their associated design methods and tools in electronic design. It is = a >multi-facetted event that offers a wonderful opportunity to get an = up-to- >date information thanks to hosting several events at the same time and = the >same location. > >The VHDL Users' Forum in Europe (VUFE) is the European event that = gathers >VHDL users since its inception in 1989. It provides a complete = snapshot on >the status of the practical use of the VHDL hardware description = language >in the electronic design community, covering the aspects of (formal) >specification, modeling, simulation, synthesis, and testing. It also >provides an update on the latest developments and trends on the = evolution >of the language throughout standardization processes, and an = opportunity to >contribute to these efforts. > >The Workshop on Virtual Component Modeling (VCM), formerly known as = the >Workshop on Libraries, Component Modeling, and Quality Assurance, is = the >European event on all aspects related to the development and the use = of >virtual components in electronic design. These include modeling, >information and knowledge representation, verification, library >development, reuse, intellectual property, collaborative engineering, = and >web-based applications. This is the third occurrence after two = successful >events in 1995 and 1997. > >The Workshop on System-Level Design Language (SLDL) is held 1-2 times = a >year since 1996. It addresses the need to develop general = industry-wide >consensus on the key problems facing the design of electronic systems = as >they relate to description of design intent for use by EDA tools, and = to >arrive at a consensus view on how these problems should be addressed >through coordinated industry standards development. For the purposes = of >this effort, a system can include digital hardware, analog hardware, >software, and mechanical components. > >In addition, the Forum will provide several half-day tutorials on = selected >hot topics before the technical sessions and several hands-on = tutorials in >parallel with technical sessions that will allow attendees to practice = EDA >tools with the help of instructors from EDA companies. Finally, the = Forum >will also host several working groups meetings of the IEEE Design >Automation Standards Committee (DASC). These meetings are open to = everybody >interested. > >TOPICS OF INTEREST > >Authors are invited to submit original technical contributions = describing >methods, tools, and design practices related, but not limited, to the >following list of topics: > >VUFE: >- VHDL and DSP design >- VHDL and hardware/software co-design and co-verification >- VHDL and automatic synthesis >- VHDL and mixed-signal/RF design >- VHDL and links to back-end design >- VHDL and formal verification >- VHDL simulation performance >- VHDL front-end tools >- VHDL and system design >- VHDL and performance modeling and estimation >- VHDL and test >- VHDL modeling for core base design and reuse >- VHDL interoperability with other languages >- Role of VHDL in industrial applications > (e.g. telecommunications, automotive, aerospace) >- VHDL and engineering project management >- VHDL future (e.g. PLI, RTL subset, object oriented extensions, > interface modeling, graphical semantics) >- VHDL standardization >- VHDL and education > >VCM: >- Design and technology reuse: reuse in incremental and hierarchical > design, reuse of functions and components, reuse of information, > models, and libraries, lessons from SW engineering, rapid = prototyping, > distributed simulation >- Component modeling: libraries, complex component models, board-level > modeling & verification, modeling for synthesizable models, > mixed-signal models, modeling hard macros >- Electronic Data Books: application of SGML, EDBs on the Web >- Digital engineering libraries: global engineering networks, > organisation of engineering knowledge, Web-based engineering = services, > network-based information brokers, collaborative engineering >- Intellectual property protection & encryption, legal issues >- Industrial initiatives (e.g. VSIA, Pinnacles/ECIX, OMF/OMI) > and large-scale R&D projects (e.g. ESPRIT, RASSP) >- Standards and emerging standards > >SLDL workshop: >Contributions for the SLDL Workshop should be sent to the SLDL = European >representative. More information on this workshop is available in the = ECSI >Web site at http://www.ecsi.org/. > >REQUIREMENTS FOR SUBMISSIONS OF CONTRIBUTIONS > >Each submission should include a cover page and the proposed = contribution. >The cover page should include the complete coordinates of each author, = and >the name of the presenter if the contribution is accepted. The = contribution >should include 1) the name of the event (VUFE or VCM) and a list of = topics >that most closely match its content, 2) a title, and 3) either an = extended >abstract of approximately 500-1000 words, or a full paper not = exceeding 12 >pages in 12pt, one column format. Contributions should include the >descriptions of key ideas, results, contributions, limitations, and >experimental conditions. > >Accepted authors are NOT required to prepare a full-length final = paper. >Slides handouts are accepted as final versions for contributions that = have >been submitted as an extended abstract. Abstract-only final versions = are >also accepted for confidential presentations that are subject to non- >disclosure constraints. All accepted contributions will be bound and >distributed at the Forum. Outstanding full-length accepted papers will = be >candidate to be published in an edited book (publisher yet to be >announced). > >OPEN DISCUSSION SESSIONS > >The Forum will offer attendees a way to discuss hot topics in a lively >fashion. Proposers are invited to chair an open discussion session and = to >give a 10 minutes presentation on the first day of the event (VUFE or = VCM) >to let attendees think of the issues. The actual session will take = place >the day after, at the earliest, during the afternoon or the evening. >Attendees will be able to prepare some material on site. Proposers are >invited to send a short description of the proposed discussion theme. = The >selected themes will be announced in the final program. > >TUTORIALS AND WORKING GROUP SESSIONS > >Proposals for half-day tutorials (introductory, advanced, or expert = level), >hands-on tutorials, and working group sessions are invited. Hands-on >tutorials from EDA vendors are invited to be given in a 20 workstation = room >in parallel with technical sessions. > >FORM OF SUBMISSIONS > >Interested authors are invited to send the requested information in >electronic format to Alain Vachoux, FDL General Chair. Preferred electr= onic >formats are: RTF, PDF, Postscript, or plain ASCII. Compressed = submissions >with GNU gzip, Unix compress, PKZip are also accepted. > >FORUM COMMITTEE > >FDL General Chair: > Dr. Alain Vachoux > Swiss Federal Institute of Technology > Integrated Systems Center > CH-1015 Lausanne, Switzerland > phone/fax: +41 21 693 6984 / 4663 > mailto:alain.vachoux@epfl.ch > >VUFE Program Chair: > Prof. Donatella Sciuto > Dip. di Elettronica e Informazione > Politecnico di Milano > Piazza L. da Vinci 32 > I-20133 Milano, Italy > phoen/fax: +39 2 2399 3662 / 3411 > mailto:sciuto@elet.polimi.it > >VCM Program Chair: > Prof. Przemyslaw Bakowski > IRESTE, University of Nantes > Institut de Recherche > Rue C. Pauc > La Chantrerie - BP 60601CP > F-44306 NANTES, France > phone/fax: +33 2.4068 3079 / 30 66 > mailto:pbakowsk@ireste.fr > >SLDL European Representative: > Dr. Jean Mermet > ECSI, Parc Equation > 2, avenue de Vignate > F-38610 Gi=E8res France > phoen/fax: +33 4 76 63 4934 / 42 8787 > mailto:jean.mermet@imag.fr > >SLDL Chair: > Dr. Dave Barton > Intermetrics, Inc. > 1595 Spring Hill Rd., Suite 600 > Vienna, VA 22182, USA > phone/fax: +703-827-2606 / 5560 > mailto:dlb@wash.inmet.com > > > >
Donatella Sciuto Dipartimento di Elettronica e Informazione Politecnico di Milano P.zza L. da Vinci 32 20133 Milano, ITALY ph. 39-2-2399-3662 fax 39-2-2399-3411 e-mail: sciuto@elet.polimi.it
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