This is a follow up announcement that a series of workshops will be held on
the Chip Hierarchical Design System (CHDS) Technical Data (CHDStd) draft
standard. Specifically, the next CHDStd workshops are being held at the
following times and places:
ASP-DAC-98:
Date: February 9 and 10, 13:00-18:00
Place: Pacifico Yokohama.
Room: Exact room will be announced.
DATE-98:
Date: February 22 (Tentative - This is still being confirmed.)
Time: 10:00am to 5:00pm
Place: Thomson - Exact location and details of how to get there
will be published shortly.
CHDStd Workshops are being given in order to help designers and EDA
professionals understand what CHDStd is, what it is targeted at, and how
it can be applied to EDA systems.
The purpose of the workshops is also to get industry ready to review the
CHDStd draft standard as the CHDStd standard goes through upcoming SI2,
IEEE DASC, and IEC TC93 standardization review cycles.
The workshops are open to anyone who wishes to attend.
Please send a email reply to one of the organizers listed later in this
message if you are planning or considering attending one of these workshop.
--Steve Grout
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WORKSHOP AGENDA:
The following is a planned agenda for the upcoming February CHDStd
workshops. If you plan to attend one of workshops, please send a email or
voice message to one of the below Workshop organizers so that we may
provide adequate space.
MEETING TITLE: Workshop on the CHDStd Hierarchical Design Standard for
Deep Submicron Chip Design
CHDSTD WORKSHOP GOALS:
The CHDStd Workshop will introduce attendees to the design, information
coverage, characteristics, and specifications of CHDStd, and brief
attendees the capabilities of the Application Programming Interface (API)
software of the standard.
The workshop is being conducted as part of both informing and getting
comments from industry as part of the process of standardizing CHDStd
within the IEEE and IEC TC93.
AGENDA: CHDStd material to be covered includes the following:
1. Brief overview of the SEMATECH 0.25u - 0.18u hierarchical chip
design system program requirements for CHDStd:
2. Overall CHDStd Architecture:
- Data Model
- Central Delay Architecture
- Application Programming Interface (API)
3. New novel CHDStd EDA design functions
4. CHDStd information model
5. Examples of using the CHDStd Application Programming Interface (API)
for a typical EDA applications
TARGET WORKSHOP PARTICIPANTS:
The intended participants for this workshop includes:
Leading edge high performance IC designers
EDA system integrators
EDA application developers
CHDStd WORKSHOP ORGANIZERS:
Name: Donald Cottrell
Company: Silicon Integration Initiative, Inc.
Austin, TX, 78759
Phone: (512) 342-2244 X22
Email: cottrell@cfi.org
Name: Steve Grout
Company: SEMATECH
Austin, TX 78741
Phone: (512) 356-7071
Email: steve.grout@sematech.org
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CHDStd BACKGROUND:
The Chip Hierarchical Design System Technical Data (CHDStd) draft standard
includes capability for a number of advanced EDA capabilities, including
design planning, accurate parasitic model extraction, and signal integrity
verification.
CHDStd is a open EDA design proposed draft standard upon which high
performance deep submicron chip design tools are integrated.
The CHDStd standard is being developed jointly by SEMATECH and Silicon
Integration Initiative (SI2) and supports a number of advanced critical EDA
requirements including:
- A design data scope that includes connectivity, electrical data,
physical data, timing and constraints;
- Design hierarchy and incremental access to data;
- Central delay architecture;
- Efficient, application-selected views of the data.
- A common design model representation standard and access definition for
use in the design of large complex integrated circuits (chips) (28M
transistors or more) designed for 0.25u - 0.18u and below technologies,
being designed by large, multi-team design organizations.
- Is based on a proven API design representation base technology that is
in use for leading edge chip designs by IBM and that has been transferred
to SI2 from IBM.
- Is being developed by and is jointly sponsored SEMATECH and SI2.
- An Application Procedure Interface (API) (software) call-based standard.
- Is a key part of the CHDS advanced chip design system being developed
for SEMATECH and its member companies by Synopsys, Lucent Technologies
(formerly Bell Labs), Cadence Cooper and Chyan Technology, OEA
International, Ultima Interconnect Technology. (SEMATECH member companies
include AMD, Digital Equipment Corporation, HP, IBM, Intel, Lucent
Technologies, Motorola, National Semiconductor, Rockwell, and Texas
Instruments)
Downloadable initial CHDStd Draft Standard/Specification:
The complete text of the Draft CHDStd Specifications is available in PDF
(Adobe Acrobat) format (with the exception of the EXPRESS-G of the
Operational Model which is in PostScript format) and available as two
downloadable .ZIP files.
Introduction and Express
http://www.si2.org/CHDStd/ZIP/CHDStd_DOC2.zip
APIs
http://www.si2.org/CHDStd/ZIP/CHDStd_DOC1.zip
For additonal background on CHDStd, two additional URLs are of interest:
Requirements for the Chip Hierarchical Design System (CHDS) and CHDStd
http://www.sematech.org/design/ecad
Other CHDStd development information
==========================================================
CHDStd INDUSTRY REVIEW WORKSHOP SCHEDULE:
CHDStd workshops have been or will be at the following locations and times:
10/23/97 - EIA Headquarters, 2500 Wilson Blvd, Arlington, VA 22201-3834,
at 5:30pm to 8:30pm, just following the EDA Standards Roadmap kickoff
industry meeting.
10/24/97 - Intermetrics, 1595 Spring Hill Rd., Suite 600, Vienna, VA
22182, at 1:00pm to 4:00pm, as part of the IEEE DASC meetings being held
there.
11/9/97 - Doubletree Inn (formerly Red Lion Inn), San Jose, CA., at 1:00pm
to 5:00pm, the Sunday before ICCAD-97.
2/10/98 - Tokohama, JP, co-located with ASP-DAC-98. Specific date,
time, and location to be announced later.
2/24/98 - Paris, FR, co-located with DAT-E-98. Specific date, time, and
location to be announced later.
- We will post an agenda shortly for the upcoming meetings so that you may
make a more informed decision as to attending.
- If you do plan to attend, it will help us to provide adequate meeting
space if you will tell us via a email reply, voice mail, or fax to
Steve Grout
SEMATECH
2706 Montopolis Dr, Austin, TX 78717-6499
Phone: (512)356-7071 Fax: (512)356-7080
email: grouts@bootskut.eng.sematech.org or Steve.Grout@SEMATECH.Org
or
Don Cottrell
SI2
4030 West Braker Lane - Suite 550
Austin, TX 78759
Phone: (512)342-2244, X22, FAX: (512)342-2037
email: cottrell@si2.org
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