I didn't see a reply to this yet, so let me try to provide a little
information. I've CC'd a couple people who should be able to keep me
honest.
These SDF statements are legal in both OVI versions 2.1 and 3.0:
(SETUP TWN (posedge CLK) (0.271:0.513:1.541))
(SETUP TWN[9:0] (posedge CLK) (0.271:0.513:1.541))
However, as you've discovered, not all SDF annotators can handle
annotations specified this way. I'm sure some of them require you to
mention each bit individually, in other words:
(SETUP TWN[0] (posedge CLK) (0.271:0.513:1.541))
(SETUP TWN[1] (posedge CLK) (0.271:0.513:1.541))
...
(SETUP TWN[9] (posedge CLK) (0.271:0.513:1.541))
On the Verilog side, some SDF annotators may run into simulator
limitations that stem from ambiguities in the Verilog 1364 standard.
For example, 1364 isn't specific about what this means:
input [7:0] DATA, CLK;
...
$setup (DATA, CLK, 6);
Is this one setup check? Eight? Sixty-four? What the SDF annotator
should do depends upon the answer to this question. (Just for the
record, Verilog-XL and NC-Verilog interpret this as sixty-four setup
checks. With Verilog-XL you have to also include the
+expand_specify_vectors command line option or `expand_specify_vectors
compiler directive to annotate to the individual checks, otherwise you
can only annotate to it as if it were a single setup check.)
There are other ambiguities. For example, how should this SDF
construct be interpreted:
(INTERCONNECT DRVERS[31:0] LDS[31:0] (7))
Is it 32 interconnect delays? Or 1024? Is it a single wire with
multiple sources and loads, or multiple wires each with a single
source and a single load? Or is it some combination of these?
It is easy to see how things can go wrong in this case. If the SDF
annotator assumes 1024 delays on a multi-source net when the design is
actually only 32 parallel wires, then there'll be 992 warning
messages. If the opposite occurs then there will be 992 unannotated
source/load delays. For these reasons, the NC-Verilog SDF annotator
requires that all INTERCONNECT annotations be single bit at a time,
eg:
(INTERCONNECT DRVERS[0] LDS[0] (7))
(INTERCONNECT DRVERS[1] LDS[1] (7))
...
But other tools may make different choices.
It would be a good idea to have some definitions in the 1364 standard
regarding these issues.
Ted
======================================================================
Tanu Khanna writes:
> Hi,
> Could anybody let me know which of the following syntax for bussed ports
> is valid in SDF version 2.1 or higher.
>
> (SETUP TWN (posedge CLK) (0.271 : 0.513 : 1.541) )
>
> OR
> (SETUP TWN[9:0] (posedge CLK)(0.271 : 0.513 : 1.541) )
>
> The reason why I want to find out this is because apparently different
> simultor support different syntax.
>
> Thanks
> Tanu Khanna.
>
>
>