A SIG-VHDL event sponsored by ECSI,
co-sponsored by IFIP 10.5 *, VI, OVI, ITG, GI, GMM, IEEE,
SYNOPSYS, MENTOR-GRAPHICS, MEDEA
(*) With no financial implication
featuring:
HDL Workshop with VHDL Users' Forum in Europe (Aug. 31-Sept. 1)
Workshop on Virtual Component Design & Reuse (Sept. 1-2)
Workshop on System Specification & Design Languages (Sept. 2-3)
2ND CALL FOR CONTRIBUTIONS
IT'S NOT TOO LATE FOR YOUR SUBMISSION !
IMPORTANT DATES IN 1999
Paper or abstract contributions due: MARCH 26TH
Panel session & tutorial proposals: May 7
Notification of acceptance: June 4
Final paper contributions due: July 2
Late contributions: July 2
FDL'99: Aug 30-Sept. 3
Half-day tutorials: August 30
HDL & VUFE: Aug. 31-Sept. 1
VCDR: September 1-2
SSDL: September 2-3
The Forum on Design Languages (FDL) is the European forum to exchange
experiences and to learn about new efforts and trends in the application of
languages and their associated design methods and tools in micro-electronic
design. It is a multi-facetted event that offers a wonderful opportunity to
get up-to-date information thanks to hosting several events at the same
time and the same location, namely:
The HDL Workshop with the VHDL Users' Forum in Europe (HDL&VUFE) is the
European event that gathers together VHDL and other HDL users. It provides
a complete snapshot of the status of the practical use of the VHDL and
other hardware description languages in the electronic design community,
covering the aspects of (formal) specification, modeling, simulation,
synthesis, and testing. It also provides an update on the latest
developments and trends in the evolution of these languages through
standardization projects, and an opportunity to contribute to these efforts.
The Workshop on Virtual Component Design & Reuse (VCDR) follows up two
occurrences of the Workshop Reuse Techniques for VLSI Design in Karlsruhe
in 1997 and 1998. It is the annual event dedicated to a broad spectrum of
digital and analog VC reuse. The main objective is to present new ideas and
methodologies for reuse and IP. Contributions from industry and research
institutions will be presented from the domains of commercial systems,
upcoming development trends and standardization activities.
The workshop addresses all aspects of research and development for design
reuse and VCs at all relevant levels of abstraction.
The Workshop on System Specification & Design Languages (SSDL) continues
the SLDL workshop held 4 times (Dallas-1996, Santa Clara-1997, Barga-1997,
Lausanne-1998) and is aimed at becoming THE yearly event on this subject.
It addresses the need to develop industry-wide consensus on the key
problems met by the designers of Systems on a Chip (SoC) as they relate to
e.g. the description of design specification, functional and implementation
constraints, usability by EDA tools. It aims at developing coordinated
industry standards.
The workshop will address all topics relevant to the SoC's, that can
include digital hardware, analog hardware, software, sensors, micro-
mechanical components (MEMs), batteries, chemical captors, optical devices.
In addition, the Forum will provide several tutorials on selected hot
topics before the technical sessions and several hands-on tutorials in
parallel with technical sessions. These will allow attendees to try EDA
tools with the help of instructors from EDA companies.
Finally, the Forum will also host several working groups meetings of the
IEEE Design Automation Standards Committee (DASC). These meetings are open
to everybody interested.
ECSI fax: +33 476 42 87 87
MORE INFO ON: http://www.ecsi.org/ecsi/fdl
TOPICS OF INTEREST
Authors are invited to submit original technical contributions describing
methods, tools, and design practices related, but not limited, to the
following list of topics:
HDL & VUFE
HDL based functional verification of hardware - HDL formal verification -
HDL's for VC modeling
- HDL for mixed signal and analog design - Place of HDL's in hardware
software co-design and co-verification - Languages for DSP design - HDL in
education - HDL's related Standards - HDL simulation performances - HDL for
RF and microwaves - HDL use in industry - Role of VHDL and other
HDL's in industrial applications (e.g. telecom, automotive, aerospace)
- VHDL front-end tools - Synthesis from VHDL descriptions - VHDL and test -
Use of VHDL in
performance modeling and estimation - VHDL modeling for core base design -
VHDL interoperability
with other languages - VHDL-AMS issues - VHDL and engineering project
management - VHDL standardization - VHDL links to system level - VHDL
extensions: (e.g. PLI, object oriented extensions, interface modeling,
graphical semantics)
VCDR
- Innovative reuse methods - Design for reuse - Adaptative VC interfaces -
Reuse of analog designs
- IP legal issues - Knowledge based VC library management - Rapid
prototyping - Development and application of reuse libraries -
Availability and customization of software macros - Reuse of
re-configurable hardware macros - Generic components - Emerging standards -
Proprietary solutions - Case studies - Commercial tool environments and
prototype systems
SSDL
- Language and notations - Specification consistency - System level
verification - Specification and tracking of application or design
constraints - Price/perform. constraints - Modeling of heterogeneous
systems - Languages for reactive and/or real-time systems - Synchronous
languages - Multi-language design flow - Modeling theSoC environment -
Modeling with VHDL/AMS - Architecture mapping - Languages issues in HW/SW
co-design - System specification experiments and case studies - SLDL
standardization
PRE-FORUM TUTORIALS
Proposals for half-day tutorials are invited.
Proposals will be selected on the evidence that they can transfer in 5
hours a comprehensive knowledge of the topics of interest they are
addressing.
PANEL SESSIONS
Proposals for panels should clearly state the topic, a title, the
composition of panel members and, if available, the name of the
panelists, their affiliations and domain of expertise. The panels will
last no more than one hour and 30 minutes and involve an average of 4
panelists and a moderator.
HANDS-ON-LABS AND WORKING GROUP MEETINGS
Hands-on-labs from EDA tool providers (commercial and academic) are invited
to be given on Unix or PC workstations, in parallel with technical
sessions. A title and a summary of the lab contents are required.
Working group meetings are welcome, in conjunction with the event or on
Saturday Sept. 4. Applications should be directed to the FDL Organization
Co-Chair as soon as possible to facilitate room allocation.
REQUIREMENTS FOR SUBMISSION OF CONTRIBUTIONS
Each submission should include a cover page and the proposed contribution.
The cover page should include the complete coordinates of each author, and
the name of the presenter if the contribution is accepted. The contribution
should include
1- the name of the workshop (HDL & VUFE, VCDR, SSDL) and a list of topics
that most closely match its content,
2- a title, and
3- either an extended abstract of approximately 1000-2000 words (abstracts
not in this format will be rejected),
or a full paper not exceeding 10 pages in 12pt, one column format.
Contributions must include descriptions of key ideas, results,
contributions, limitations, experimental conditions (if applicable), and
appropriate references to other related works.
Some outstanding late contributions can be submitted until July 2. Late
contributions will not exceed 20% of all accepted contributions.
Accepted authors are NOT required to prepare a full-length final paper.
Slide handouts are accepted as final versions for contributions that have
been submitted as an extended abstract. Abstract-only final versions are
also accepted for confidential presentations that are subject to
non-disclosure constraints. Accepted contributions will be bound and
distributed at the Forum. The best accepted papers will be candidate to be
published in an edited book (publisher yet to be announced).
FORM OF SUBMISSIONS
Interested authors are invited to send the requested information in
electronic format to both
Jean Mermet, FDL General Chair and
Ralf Seepold, FDL Program Chair
Preferred electronic formats are in this order: PDF, RTF, Postscript,
Compressed submissions with GNU gzip, Unix compress, PKZip are also
accepted.
CONTACTS
FDL GENERAL CHAIR
Dr. Jean Mermet
Laboratoire TIMA
ECSI, Parc Equation
France
fax : +33 4 76 42 87 87
jean.mermet@imag.fr
FDL ORGANIZATION CO-CHAIR
Dr. Anne Mignotte
Ecole Normale Supérieure de Lyon
France
fax : +33 4 72 72 80 80
anne.mignotte@ens-lyon.fr
FDL PROGRAM CHAIR
Dr. Ralf Seepold
FZI Karlsruhe
Germany
fax : +49 (0)721/9654-477
seepold@fzi.de
HDL & VUFE CHAIR
Prof. Donatella Sciuto
Italy
fax : +39 02 2399 3411
sciuto@elet.polimi.it
VCDR CHAIR
Dr. Ralf Seepold
SSDL CHAIR
Prof. Eugenio Villar
Spain
fax : +34 9 42 20 1873
villar@teisa.unican.es
TUTORIAL CHAIR
Prof. Wolfgang Rosenstiel
Germany
fax : +49 7071 29 50 62
rosenstiel@informatik.uni-tuebingen.de
+FDL PAST CHAIR
Dr. Alain Vachoux
Xemics SA, Switzerland
FDL STEERING BOARD CHAIR
Prof. Wolfgang Nebel
Oldenburg University, Germany
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