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Dear Colleague,
The VITAL Technical Action Group (TAG) announces the completion of Draft 1
of the IEEE 1076.4 VITAL 1999 specification. If you are at the
International HDL Conference, please plan to join us at this important
meeting to get your review copy of the VITAL 99 specification.
Subject: VITAL 99 Working Group Meeting (open to the public)
Where: Santa Clara Convention Center, Room GA-1
When: Friday, April 9, 1999
Time: 9:30am - 12:30am
In conjunction with the International HDL Conference (see conference details
and registration information below), there will be an IEEE 1076.4 VITAL
Working Group meeting to launch the review of the proposed VITAL 1999
standard.
All attendees to this meeting will be given a bound copy of the first draft
of the VITAL 1999 standard for review and comment. You must participate in
this meeting to get this review copy. VITAL 99 includes new features and
many enhancements to the 1995 standard. The agenda for this meeting will
include a discussion on these features.
We will also announce VITAL 99 code download instructions at the meeting for
you to use this with your VHDL simulators.
Seating is limited and so are the copies of the VITAL 99 specification. The
specification will be given out on a first come first serve basis.
Agenda:
-------
9:30am - 9:40am Introduction
9:40am - 10:55am VITAL 99 Feature Enhancements
- Multi-source interconnect
- Additional generics to control
‘X’ generation and message
reporting for glitches and
timing constraints.
- SKEW constraint check
- Timing constraint checks
feature enhancements
- Negative constraint calculation
enhancement for vector signals
to support memory models
- Fast delay path disable
- Negative glitch preemption
10:55am - 11:55am Memory Model
11:55am - 12:15pm Question & Answers
12:15pm - 12:30pm Wrap-up / Close
-----------------------------------
The 8th Annual INTERNATIONAL HDL CONFERENCE & EXHIBITION
(formerly IVC/VIUF)
April 6-9, 1999 - Santa Clara Convention Center, Santa Clara, CA
Tutorials April 6 & 9
Conference and Exhibition April 7 & 8
Register on-site at the Santa Clara Convention Center
Registration Hours: April 6-9 7:30am-5:00pm
HDL Con '99 is the conference for designers who use HDLs in their design
process. Learn the latest trends in ASIC SOC design, FPGA and PLD processes.
Technical programs include papers, tutorials, and panel sessions which will
investigate innovative Verilog and VHDL design techniques and cover topics
like HW/SW co-design, system emulation, synthesis, formal verification and
more! A wide range of 1/2 day tutorial sessions, presented by experts in
their respective fields, offer an in depth look at the cutting edge
technologies and processes relating to the use of HDLs for SOC design.
The exhibition features EDA vendors showing the latest HDL tools for the
development of consumer electronics, telecommunications and computers. You
will find the design tools to improve your knowledge of the use of HDLs in
your design flow.
Exhibitors include:
Aldec, Avant!, Axis Systems, C Level Design, Cadence, Chronology, Denali,
Escalade, Exemplar Logic, Fintronic USA, FTL Systems, Genesys Testware,
HDAC, HP, Ikos, ISD, Kluwer Academic Publishers, Library Technologies,
Mentor Graphics, Model Technology, Novas, Sente, Seva Technologies, Silicon
Forest Research, Simpod, Simucad, Summit Design, Surefire Verification,
Synapticad, Synopsys, Synplicity, SynTest, Technically Speaking, TM
Associates, Transeda, Translogic USA, VeriBest, Verisity, Veritools,
Verplex, Verysys Design Automation, Viewlogic, Western Digital Design
Center and Willamette HDL.
NEW AT HDL CON' 99
* Single session pass registration.
* Register 2 people and receive the third registrant for FREE!
* Register for only one tutorial session and see the exhibits as part of
the package.
* Location, Santa Clara Convention Center... It's close to work or
home! Swing by for a 1/2 day of sessions, networking, exhibits, and
speak to vendors in one location!
Stop by the web site for more information and on-line registration.
For more information contact the HDL Conference office at
5305 Spine Road, Suite A
Boulder, CO 80301
Tel: 303-530-4562
Fax: 303-530-4334
e-mail: info@hdlcon.org
1999 INTERNATIONAL HDL CONFERENCE & EXHIBITION - PAPER AND PANEL SESSIONS
SESSION 1 - INTELLECTUAL PROPERTY
Wednesday 10:30 to 12:00 Ballroom G
Session Chair: Paul Menchini - OrCAD, Durham, NC
1.1 RETARGETING AN IP CORE TO FPGA - AN EFFICIENT APPROACH
Dattatri Mattur, Mahesha S - Integrated Intellectual Property, Santa Clara,
CA
1.2 A METHODOLOGY FOR MULTI-LINGUAL IP AUTHORING
Sashi Obilisetty, - DualSoft LLC, Nashua, NH
Mahesh Girkar - Consultant, Nashua, NH
1.3 AGP CORE: A CASE STUDY IN HDL BASED IP METHODOLOGY
Samir Palnitkar - Integrated Intellectual Property, Inc., Santa Clara, CA
SESSION 2 - TIMING ISSUES
Wednesday 10:30 to 12:00 Ballroom H
Session Chair: Tony O'Conner - Avid Technology, Inc., Tewksbury, MA
2.1 NEGATIVE CONSTRAINTS: ISSUES WITH VITAL/VERILOG
Ravi Kumar - Cadence Design Systems Inc., San Jose, CA
2.2 CORRECT METHODS FOR ADDING DELAYS TO VERILOG BEHAVIORAL MODELS
Clifford E. Cummings - Sunburst Design, Beaverton, OR
2.3 FUNDAMENTAL PRINCIPLES OF MODELING TIMING IN HARDWARE DESCRIPTION
LANGUAGES FOR DIGITAL SYSTEMS
Sumit Ghosh - Arizona State Univ., Tempe, AZ
PANEL 1 - RTL DESIGN PLANNING AND PROTOTYPING: ARE WE THERE YET?
Wednesday 1:30 to 3:00 Room A2
Organizer: Tony Kasovich - Sente, Inc., Santa Clara, CA
Moderator: Jim Lipman - EDN Magazine, Livermore, CA
Abstract:
Everyone in the electronics industry agrees that changes must be made to the
way design is done, particularly as it struggles with the complexity of deep
submicron design. Register-transfer level (RTL) design-planning tools hold
promise. However, few are commercially available today or are used in a
production environment. In addition, the definition of RTL design planning
continues to confuse. Are design-planning tools doing logic design or
physical design, or both? What is possible? What's coming?
Panelists will present differing views on the value of and requirements for
RTL design planning, successes and failures using commercially available
tools. This panel, composed of designers, CAD managers and EDA
manufacturers, will address compelling issues, including what works and what
does not in a real-world design environment. It is to be moderated by Jim
Lipman, EDA and ASIC Technical Editor for EDN Magazine.
Panelists:
Dave Allen - Sente, Inc.
Anand Anandkumar - Cadence, Digital IC-SOC Group
Rod Dudzinski - Aristo Technology
Guy Dupenloupe - LSI Logic
SESSION 3 - VHDL DESIGN EXPERIENCES
Wednesday 3:30 to 5:00 Ballroom G
Session Chair: Praveen Chawla - EDAptive Computing, Inc., Dayton, OH
3.1 VHDL DESIGN OF AN INTELLIGENT FUZZY LOGIC CONTROLLER FOR SYNCHRONOUS
GENERATOR SETS IMPLEMENTED IN FPGA
Marcian Cirstea, J. Khor,<B> M. McCormick - De Montfort Univ., Leicester, Uk
L. Haydock - Newage International Ltd., Stamford, Uk
3.2 VHDL MODELING OF A DIGITAL MODEM FOR LEO SATELLITE COMMUNICATION
Narcis Simon,<B> Juanjo Noguera,<B> Carles Ferrer - CNM-UAB, Bellaterra,
Spain
3.3 ETHERNET LAN MODELING WITH VHDL
Reza Purtoosi,<B> Zainalabedin Navabi - Univ. of Tehran, Tehran, Iran
SESSION 4 - VERILOG SYNTHESIS
Wednesday 3:30 to 5:00 Ballroom H
Session Chair: Mike Ciletti - Univ. of Colorado, Colorado Springs, CO
4.1 FSMDESIGNER: COMBINING A POWERFUL GRAPHICAL FSM EDITOR AND EFFICIENT HDL
CODE GENERATION WITH SYNTHESIS IN MIND
Lars Rzymianowicz - Technische Informatik Univ. Mannheim, Mannheim, Germany
4.2 A STANDARD FOR VERILOG HDL RTL SYNTHESIS
J. Bhasker - Cadence Design Systems, Allentown, PA
4.3 BLOCKING AND NON-BLOCKING ASSIGNMENTS IN EXPLICIT AND IMPLICIT STYLE
VERILOG SYNTHESIS
Mark G. Arnold, Jerry J. Cupal - Univ. of Wyoming, Laramie, WY
James D. Shuler - SUNY College at Brockport, Brockport, NY
PANEL 2 - NEW TECHNIQUES TO BOOST FUNCTIONAL VERIFICATION EFFICIENCY
Thursday 8:30 to 10:00 Room A2
Organizers: Tedd Corman - Viewlogic Systems, San Jose, CA
Steve Wang - Axis Systems, Sunnyvale, CA
Moderator: Richard Goering - EETimes, Felton, CA
Abstract:
With integrated circuits manufacturing outpacing traditional verification
techniques, all companies are facing increasing pressure to verify their
design efficiently. With emerging new technologies from reconfigurable
computing to formal verification and testbench automation, can these new
techniques help bridge the verification knot? Are these new techniques
enough? How easy and viable are these new techniques?
This panel brings together experts from leading verification companies and
customers who are using new technologies to obtain efficient verification
throughput. Discussion topics include advantages and disadvantages of each
new technology, circumstances that warrant the new technology to be deployed
and the success rate from actual customer usage model.
Panelists:
Steven Wang - Axis Systems, Sunnyvale, CA
Tom Rathje - Chrysalis Symbolic Design, North Billerica, MA
Ghulam Nurie - Synopsys, Palo Alto, CA
Chris Malachowsky - Nvidia Corporation, Sunnyvale, CA
Jim Gateley - Sun Microsystems, Palo Alto, CA
Vallath Nandakumar - Advanced Micro Devices, Sunnyvale, CA
SESSION 5 - CO-SIMULATION
Thursday 10:30 to 12:00 Ballroom G
Session Chair: Mike Baird - Willamette HDL, Inc., Beaverton, OR
5.1 AN EXPERIENCE USING A NEW METHODOLOGY FOR THE CODESIGN OF EMBEDDED HW/SW
SYSTEMS
Giuseppe Mangioni - Univ. di Catania, Catania, Italy
5.2 MULTITASKING HARDWARE/SOFTWARE CO-SIMULATION ON DUAL PROCESSOR NT
WORKSTATIONS
Ray Khorram - Pixel Magic, Inc., Andover, MA
5.3 HARDWARE/SOFTWARE CO-SIMULATION METHODOLOGY BASED ON TWO ALTERNATIVE
APPROACHES
Kostas Pramataris,<B> G. Likakis,<B> John Kamaras - National Technical Univ.
of Athens, Athens, Greece
SESSION 6 - VERIFICATION
Thursday 10:30 to 12:00 Ballroom H
Session Chair: David Barton - Intermetrics, Inc., Vienna, VA
6.1 A DEPENDENCY GRAPH FOR VHDL DESIGN FILES AND DESIGN UNITS AND ITS
APPLICATION IN A VHDL DESIGN ENVIRONMENT
Wolfgang Ecker, Jochen Mades, Thomas Schneider, Andre Windisch<B>,Ke Yang -
Siemens AG, Muenchen, Germany
6.2 COMMUNICATION AND SYNCHRONIZATION USING BOUNDED CHANNELS IN SUAVE
Peter J. Ashenden, Robert Esser - Univ. of Adelaide, Adelaide, Australia
Philip A. Wilsey - Univ. of Cincinnati, Cincinnati, OH
6.3 VHDL FOR SYNCHRONOUS ACTION SYSTEMS
Tiberiu Seceleanu - TUCS-Datacity, Turku, Finland
PANEL 3 - DESIGN REUSE - MYTH OR MAGIC
Thursday 1:30 to 3:00 Room A2
Organizer: Clifford E. Cummings - Sunburst Design,Inc., Beaverton, OR
Moderator: Steven E. Schulz - Texas Instruments, Dallas, TX
Abstract:
Increased design complexity and greater pressures to rapidly complete
product designs has driven the concept of design reuse. Design reuse offers
engineers the promise of shorter design cycles, higher quality designs and
the capture of key technologies for future re-implementation. Often
overlooked are the practical realities and challenges of reusing an existing
design. This panel, made up of designers and EDA tool vendors, will outline
the magic and/or reveal the myths associated with one of today's hottest
design topics, "Design Reuse." Panelists will present differing views on
whether reuse is a viable design solution and will attempt to highlight what
makes it successful, or outline the shortcoming of a design reuse strategy.
Panelists:
Clifford E. Cummings - Sunburst Design,Inc., Beaverton, OR
Yatin Trivedi - SEVA Technologies Inc., Fremont, CA
Janick Bergeron - Qualis Design Corp., Lake Oswego, OR
Michael Keating - Synopsys Inc., Mountain View, CA
Simon Klaver - Sagantec, Fremont, CA
SESSION 7 - LANGUAGE ISSUES
Thursday 3:30 to 5:00 Ballroom G
Session Chair: Aidan Herbert - Design Acceleration, Inc., San Jose, CA
7.1 SYSTEM VERIFICATION USING LARGE DATA PATTERNS WITH TWO-DIMENSIONAL
VERILOG
Edward A. Chavez - Compaq Computer Corporation, Houston, TX
7.2 AN RTL DESIGN VERIFICATION LINTING METHODOLOGY
Lionel Bening - Hewlett-Packard Co., Richardson, TX
7.3 INTEGRATING CODE COVERAGE ANALYSIS INTO A LARGE-SCALE ASIC DESIGN
VERIFICATION FLOW
Dennis Abts - Silicon Graphics, Inc., Chippewa Falls, WI
SESSION 8 - HDL DESIGN ENVIRONMENT ISSUES
Thursday 3:30 to 5:00 Ballroom H
Session Chair: Greg Tumbush - Wright Patterson Air Force Base, Dayton, OH
8.1 HDL MODEL PACKAGING USING OMI
Kathy McKinley,<B> Andrew Wilmot - Cadence Design Systems, Inc., Chelmsford,
MA
8.2 QUANTIFYING DESIGN REUSE: AN HDL-BASED DESIGN EXPERIMENT
Yutana Jawchinda, Hideaki Kobayashi - Univ. of South Carolina, Columbia, SC
8.3 THE PHILOSPHY OF MEADE A MODULAR, EXTENSIBLE, ADAPTABLE DESIGN
ENVIRONMENT
Gary Spivey - Dept. of Defense, Ft. Meade, MD
Kazuo Nakajima - Univ. of Maryland, College Park, MD
-- Dennis Brophy Email: dennisb@model.com Director of Strategic Business Development Phone: +1 (503) 526-1694 Model Technology Inc. Fax: +1 (503) 526-5473 10450 SW Nimbus Ave, Suite R Mobile: +1 (503) 706-8987 Portland, OR 97223-4347 Home Fax: +1 (503) 579-2664------=_NextPart_000_002B_01BE7BCF.09B29DA0 Content-Type: application/octet-stream; name="Dennis B. Brophy.vcf" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="Dennis B. Brophy.vcf"
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