If you're turning on VITAL acceleration, the VitalBUF procedure should not be within
the WireDelay block. Try moving it outside. Also, if you turn off VITAL acceleration,
the model ought to work as it's written.
It also might not like the non-use of PAD_ipd in the VitalWireDelay. Better to
switch the usages of PAD_tmp and PAD_ipd.
Russ Vreeland
Free Model Foundry
>
> Thanks in advance.
>
>
> ******** SolutionWare(TM) for ASIC Library Development ********
> Dr. Mehmet A. Cirit Phone: (408) 741-1214
> President (408) 221-7569
> Library Technologies, Inc. Fax : (408) 867-2753
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>
>
>
> -- vitalgen patch-level 1.131-r 10/30/98 00:28:08
> -- Copyright 1994-1998 Library Technologies, Inc.
> library IEEE;
> USE IEEE.std_logic_1164.all;
> USE IEEE.VITAL_timing.all;
> USE IEEE.VITAL_primitives.all;
> -- ENTITY declaration
> entity pld00d is
> generic(
> tpd_PAD_C : VitalDelayType01 := (0 ns, 0 ns);
> tpd_ENN_C : VitalDelayType01 := (0 ns, 0 ns);
> tipd_PAD : VitalDelayType01 := (0 ns, 0 ns);
> tipd_ENN : VitalDelayType01 := (0 ns, 0 ns);
> XGenerationOn : Boolean := TRUE;
> InstancePath : String := "+");
>
> port(
> PAD : in std_logic := 'U';
> ENN : in std_logic := 'U';
> C : out std_logic);
> attribute VITAL_LEVEL0 of pld00d : entity is TRUE;
> end pld00d;
>
> architecture Level1PinToPinDelay of pld00d is
> -- declare one internal signal for each IN and INOUT port
> signal PAD_ipd : std_logic := 'X';
> signal PAD_tmp : std_logic := 'X';
> signal ENN_ipd : std_logic := 'X';
> constant pullupMap : VitalResultZMapType := ('U','X','0','1','H');
> constant pulldownMap : VitalResultZMapType := ('U','X','0','1','L');
> -- constant triregMap : VitalResultZMapType := ('U','X','0','1','S');
> constant busholdMap : VitalResultMapType := ('W','W','L','H');
> attribute VITAL_LEVEL1 of Level1PinToPinDelay : architecture is TRUE;
> begin
> WireDelay : block
> begin
> VitalWireDelay(PAD_tmp,PAD,tipd_PAD);
> VitalBUF(q => PAD_ipd, a => PAD_tmp, ResultMap => pullupMap);
> VitalWireDelay(ENN_ipd,ENN,tipd_ENN);
> end block;
>
> VitalBehavior : Process(PAD_ipd,ENN_ipd)
> VARIABLE internalNet1 : std_ulogic;
> VARIABLE C_zd : std_ulogic;
> VARIABLE C_GlitchData : VitalGlitchDataType;
> begin
> --Functionality :
> --C = !ENN & PAD
> internalNet1 := VitalINV(ENN_ipd);
> C_zd := VitalAND2(internalNet1, PAD_ipd);
> --PathDelay :
> VitalPathDelay01(
> OutSignal => C,
> OutSignalName => "C",
> OutTemp => C_zd,
> paths => (
> 0 => (ENN_ipd'last_event,tpd_ENN_C,TRUE),
> 1 => (PAD_ipd'last_event,tpd_PAD_C,TRUE)
> ),
> GlitchData => C_GlitchData,
> DefaultDelay => VitalZeroDelay01,
> Mode => OnEvent,
> Xon => TRUE,
> MsgOn => TRUE,
> MsgSeverity => WARNING
> );
> end process;
> end Level1PinToPinDelay; -- architecture behavior
>