The code below compiled using:
Model Technology ModelSim EE vcom 5.2d Compiler 1999.01 Jan 14 1999
I have not had a chance to test it. I believe it functions the same as
was indended in the pld00d model.
Raymond Steele
rsteele@ieee.org
--------------------------------------------------------------------------------
-- File Name: fmfandApuEn.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 1999 Free Model Foundry
-- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation.-- -- MODIFICATION HISTORY:-- -- version: | author: | mod date: | changes made: -- V0.1 R. Steele 99 ARR 23 Initial coding -------------------------------------------------------------------------------- -- PART DESCRIPTION:-- -- Library: ASIC_PRIMS -- Technology: NOT ECL -- Part: ANDApuEn-- -- Desciption: Gate A and ENNeg. A can take 'Z' (pulled up). -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL;ENTITY fmfandApuEn IS GENERIC( -- tipd delays: interconnect path delays tipd_P0 : VitalDelayType01 := VitalZeroDelay01; tipd_A : VitalDelayType01 := VitalZeroDelay01; tipd_ENNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays TPD_A_Y : VitalDelayType01 := VitalZeroDelay01; TPD_ENNeg_Y : VitalDelayType01 := VitalZeroDelay01; -- generic control parameters InstancePath : STRING := "/"; MsgOn : BOOLEAN := TRUE; XOn : BOOLEAN := TRUE ); PORT ( A : IN std_logic := 'U'; ENNeg : IN std_logic := 'U'; Y : OUT std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of fmfandApuEn : ENTITY IS TRUE; END fmfandApuEn;
-------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of fmfandApuEn IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;
CONSTANT PullupMap : VitalResultZMapType := ('U','X','0','1','H');
SIGNAL Aint : std_ulogic := 'X'; SIGNAL A_ipd : std_ulogic := 'X'; SIGNAL ENNeg_ipd : std_ulogic := 'X';
BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN VitalWireDelay(A_ipd,A,tipd_A); VitalWireDelay(ENNeg_ipd,ENNeg,tipd_ENNeg); END BLOCK;
---------------------------------------------------------------------------- -- Concurrent procedures ---------------------------------------------------------------------------- a_1: VitalIDENT(q => Aint, a => A_ipd, ResultMap => pullupMap);
---------------------------------------------------------------------------- -- Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (Aint, ENNeg_ipd)
-- Functionality Results Variables VARIABLE Y_zd : std_ulogic; VARIABLE ENint : std_ulogic;
-- Output Glitch Detection Variables VARIABLE Y_GlitchData : VitalGlitchDataType;
BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ ENint := VitalINV(ENNeg_ipd); Y_zd := VitalAND2(ENint, Aint);
------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Y, OutSignalName => "Y", OutTemp => Y_zd, GlitchData => Y_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => Aint'LAST_EVENT, PathDelay => tpd_A_Y, PathCondition => TRUE), 1 => (InputChangeTime => ENNeg_ipd'LAST_EVENT, PathDelay => tpd_ENNeg_Y, PathCondition => TRUE) ) );
END PROCESS;
END vhdl_behavioral;