I would like to have an expert opinion concerning the following problem:
We create a small netlist which instanciates cells which have Vital models.
After having routed the netlist , the tool writes its SDF.
Each time an INTERCONNECT statement between a cell output and a primary output
of the design is encountered (which represent the interconnection delay due to
the wire between the cell ouput and the device ouput), VHDL simulators look for
a generic like this one: tipd_(device_output_port) which does not exist because
the description of the top level is not vital compliant.
Except adding some generics at the top level to satisfy the simulator, is there
any standard way used by designers to solve this problem ?
Thanks,
Best Regards,
Eric Charlet
Avant! LBU
Email eric_charlet@avanticorp.com