Subject: FW: IEEE/DATC EDP 2000 - Advance Program
From: Dennis Brophy (dennisb@model.com)
Date: Sun Mar 26 2000 - 21:59:27 PST
From: David Bishop [mailto:dbishop@eda.org]
Sent: Sunday, March 26, 2000 6:14 PM
Subject: IEEE/DATC EDP 2000 - Advance Program
Subject: IEEE/DATC EDP 2000 - Advance Program
From: "David J. Hathaway" <davidh@btv.ibm.com>
IEEE/DATC Electronic Design Processes 2000 Workshop
Advance Program
------------------------------------------------------------------------
April 26-28, 2000
http://www.eda.org/edps/edp00.html
Registration: https://secure.computer.org/conf/edp/register.htm
Early registration deadline: April 5, 2000.
Monterey Beach Hotel, Monterey, CA
Hotel reserved room block deadline: March 29, 2000.
------------------------------------------------------------------------
All talks will be 45 minutes. Speakers are asked to reserve about half
of
this time for questions and discussion.
Wednesday, 4/26
8:00-8:30 - Breakfast
Speaker Title / Topic
8:30-10 - Welcome and keynote
Keynote speaker to be announced
10:30-12:00 - Session 1 - Network Impacts on EDA
Naresh Sehgal, Intel Impact of the Internet on EDA
Electronic Component Efforts of
Don Cottrell, SI2 Rosetta Net and ECIX and their
impact on coming design flows
12:00-1:00 - Lunch
1:00-3:15 - Session 2 - Verification Methodologies
Dennis Brophy, Mentor Graphics Model Sim
Alec Stanculescu, Fintronic Simulation Farm
Peter van den Hamer, Philips Research
Laboratories A System Simulation Framework
3:45-5:15 - Session 3 - Distributed / Parallel Design Environments
Nancy Nettleton, Sun Compute Farms
Bruce Winter, IBM (presented by David A Client-Server Based
Architecture
Hathaway) for Parallel Design Query and
Analysis
6:30 - Dinner
Thursday, 4/27
8:00-8:30 - Breakfast
Speaker Title / Topic
8:30-10:00 - Session 4 - Physical Design Methodologies
Effects of Physical Design /
Logic
Dave Lackey, IBM Microelectronics Synthesis Integration on ASIC
Methodology
Ram Sunder, Pradeep Buddharaju, Physical Design Methodology for
Khalil Siddiqui, Santhosh Pillai, High Performance
System-on-a-Chip
Madhavi Tagare and Robert Farmer Solutions for Multimedia
Applications
10:30-12:00 - Session 5 - Effects of Physical Design / Logic
Synthesis
Integration on ASIC Methodology
Panelists:
* Patrick Groeneveld, Magma Panel: Effects of Physical
Design /
* Dave Lackey, IBM Logic Synthesis Integration on
ASIC
Microelectronics Methodology
* Dwight Hill, Synopsys
* Bob Stear, Intel
12:00-1:00 - Lunch
1:00-2:30 - Session 6 - API-Based Design Environments
The Family of API-based
standards
Don Cottrell, SI2 (OLA, ALF, LEF, CHDStd, DPCS,
...)
and how they will benefit coming
design process flows
Nagbhushan Veerapaneni The Nike Design System
3:00-5:15 - Session 7 - Design Reuse and Management
Peter van den Hamer, Philips Research Flow-Based Design Management
Rick Cook, Rik Vigeland, Mentor Cable Design Reuse Across
Diagram
Graphics Corporation Type Boundaries
Shantanu Ganguly, Intel Design Convergence Issues and
Solution Directions
6:30 - Dinner
Friday, 4/28
8:00-8:30 - Breakfast
Speaker Title / Topic
8:30-10:45 - Session 8 - Interoperability
Don Cottrell, SI2 Plug and Play Requirements for
Integrating Tools into a Flow
Joe Morrell, IBM (presented by David The IDM Data Model and its
Impact
Hathaway) on Design Flows
Discussion: Data models, and
interoperability - How do data
Workshop Participants model standards impact tool
Moderator: David Hathaway, IBM interoperability and what
requirements does this imply for
these standards?
11:15-12:00 - Wrap-up Session
Discussion on future EDP
workshops
Moderators: David Hathaway and
Margarida Jacome (workshop co-chairs) * Should EDP be expanded into
a
symposium (full papers,
proceedings)?
12:00-1:00 - Lunch and adjourn
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<head>
<title>IEEE/DATC EDP 2000 Advance Program</title>
</head>
<body text=3D"#000000" bgcolor=3D"#FFFFFF" link=3D"#0000EE"
vlink=3D"#551A=
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<center>
<b><font color=3D"#3333FF"><font size=3D+4>IEEE/DATC Electronic Design
Pro=
cesses 2000 Workshop
<br>Advance Program</font></font></b>
</center>
<hr width=3D100%>
<center>
<br>April 26-28, 2000
<br><A
HREF=3D"http://www.eda.org/edps/edp00.html">http://www.eda.org/edps=
/edp00.html</A>
<p><A
HREF=3D"https://secure.computer.org/conf/edp/register.htm">Registrat=
ion:</A> https://secure.computer.org/conf/edp/register.htm
<br><STRONG>Early registration deadline: April 5, 2000</STRONG>.
<p><A HREF=3D"http://www.montereybeachhotel.com">Monterey Beach
Hotel</A>,=
Monterey, CA
<br><STRONG>Hotel reserved room block deadline: March 29, 2000</STRONG>.
</center>
<hr width=3D100%>
<P>All talks will be 45 minutes. Speakers are asked to reserve about
half of this time for questions and discussion.
<P><table WIDTH=3D"100%" border=3D4 BGCOLOR=3D"#F0F0F0">
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#7080FF"><b><font size=3D+1
colo=
r=3D"white">Wednesday, 4/26</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#FFFFFF"><b><font
size=3D+1>8:00=
-8:30 - Breakfast</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER width=3D40%><b><font size=3D+1>Speaker</font></b>
</td>
<td ALIGN=3DCENTER width=3D60%><b><font size=3D+1>Title /
Topic</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#D0E0FF"><b><font
size=3D+1>8:30=
-10 - Welcome and keynote</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2>Keynote speaker to be announced
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#D0E0FF"><b><font
size=3D+1>10:3=
0-12:00 - Session 1 - Network Impacts on EDA</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Naresh Sehgal, Intel
</td>
<td ALIGN=3DLEFT>Impact of the Internet on EDA
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Don Cottrell, SI2
</td>
<td ALIGN=3DLEFT>Electronic Component Efforts of Rosetta Net and ECIX
and
their impact on coming design flows
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#FFFFFF"><b><font
size=3D+1>12:0=
0-1:00 - Lunch</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#D0E0FF"><b><font
size=3D+1>1:00=
-3:15 - Session 2 - Verification Methodologies</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Dennis Brophy, Mentor Graphics
</td>
<td ALIGN=3DLEFT>Model Sim
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Alec Stanculescu, Fintronic
</td>
<td ALIGN=3DLEFT><A HREF=3D"stanculescu.html">Simulation Farm</A>
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Peter van den Hamer, Philips Research Laboratories
</td>
<td ALIGN=3DLEFT><A HREF=3D"vandenhamer.html">A System Simulation
Framewor=
k</A>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#D0E0FF"><b><font
size=3D+1>3:45=
-5:15 - Session 3 - Distributed / Parallel Design
Environments</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Nancy Nettleton, Sun
</td>
<td ALIGN=3DLEFT>Compute Farms
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Bruce Winter, IBM (presented by David Hathaway)
</td>
<td ALIGN=3DLEFT>A Client-Server Based Architecture for Parallel Design
Qu=
ery and Analysis
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#FFFFFF"><b><font
size=3D+1>6:30=
- Dinner</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#7080FF"><b><font size=3D+1
colo=
r=3D"white">Thursday, 4/27</font></b>
</td>
</tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#FFFFFF"><b><font
size=3D+1>8:00=
-8:30 - Breakfast</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER width=3D40%><b><font size=3D+1>Speaker</font></b>
</td>
<td ALIGN=3DCENTER width=3D60%><b><font size=3D+1>Title /
Topic</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#D0E0FF"><b><font
size=3D+1>8:30=
-10:00 - Session 4 - Physical Design Methodologies</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Dave Lackey, IBM Microelectronics
</td>
<td ALIGN=3DLEFT>Effects of Physical Design / Logic Synthesis
Integration =
on ASIC Methodology
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Ram Sunder, Pradeep Buddharaju, Khalil Siddiqui,
Santhosh=
Pillai, Madhavi Tagare and Robert Farmer
</td>
<td ALIGN=3DLEFT><A HREF=3D"sunder.html">Physical Design Methodology for
H=
igh Performance System-on-a-Chip Solutions for Multimedia
Applications</A>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#D0E0FF"><b><font
size=3D+1>10:3=
0-12:00 - Session 5 -
Effects of Physical Design / Logic Synthesis Integration on ASIC
Methodolo=
gy</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>
Panelists:
<ul>
<LI>Patrick Groeneveld, Magma
<LI>Dave Lackey, IBM Microelectronics
<LI>Dwight Hill, Synopsys
<LI>Bob Stear, Intel
</ul>
</td>
<td ALIGN=3DLEFT><STRONG>Panel:</STRONG> Effects of Physical Design /
Logi=
c Synthesis Integration on ASIC Methodology
</td>
</tr>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#FFFFFF"><b><font
size=3D+1>12:0=
0-1:00 - Lunch</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#D0E0FF"><b><font
size=3D+1>1:00=
-2:30 - Session 6 - API-Based Design Environments</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Don Cottrell, SI2
</td>
<td ALIGN=3DLEFT>The Family of API-based standards (OLA, ALF, LEF,
CHDStd, DPCS, ...) and how they will benefit coming design process flows
</td>
</tr>
<tr>
</td>
<td ALIGN=3DLEFT>Nagbhushan Veerapaneni =
</td>
<td ALIGN=3DLEFT>The Nike Design System
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#D0E0FF"><b><font
size=3D+1>3:00=
-5:15 - Session 7 - Design Reuse and Management</font></b>
</td>
</tr>
<tr>
</td>
<td ALIGN=3DLEFT>Peter van den Hamer, Philips Research
</td>
<td ALIGN=3DLEFT>Flow-Based Design Management
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Rick Cook, Rik Vigeland, Mentor Graphics Corporation
</td>
<td ALIGN=3DLEFT><A HREF=3D"vigelund.html">Cable Design Reuse Across
Diagr=
am Type Boundaries</A>
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Shantanu Ganguly, Intel
</td>
<td ALIGN=3DLEFT>Design Convergence Issues and Solution Directions
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#FFFFFF"><b><font
size=3D+1>6:30=
- Dinner</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#7080FF"><b><font size=3D+1
colo=
r=3D"white">Friday, 4/28</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#FFFFFF"><b><font
size=3D+1>8:00=
-8:30 - Breakfast</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER width=3D40%><b><font size=3D+1>Speaker</font></b>
</td>
<td ALIGN=3DCENTER width=3D60%><b><font size=3D+1>Title /
Topic</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#D0E0FF"><b><font
size=3D+1>8:30=
-10:45 - Session 8 - Interoperability</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Don Cottrell, SI2
</td>
<td ALIGN=3DLEFT>Plug and Play Requirements for Integrating Tools into a
F=
low
</td>
</tr>
<tr>
<td ALIGN=3DLEFT>Joe Morrell, IBM (presented by David Hathaway)
</td>
<td ALIGN=3DLEFT>The IDM Data Model and its Impact on Design Flows
</td>
<tr>
<td ALIGN=3DLEFT>Workshop Participants
<br><STRONG>Moderator:</STRONG> David Hathaway, IBM
</td>
<td ALIGN=3DLEFT><STRONG>Discussion:</STRONG>
Data models, and interoperability - How do data model standards impact
tool interoperability and what requirements does this imply for these
stan=
dards?
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#D0E0FF"><b><font
size=3D+1>11:1=
5-12:00 - Wrap-up Session</font></b>
</td>
</tr>
<tr>
<td ALIGN=3DLEFT><STRONG>Moderators:</STRONG> David Hathaway and
Margarida=
Jacome (workshop co-chairs)
</td>
<td ALIGN=3DLEFT>Discussion on future EDP workshops
<UL>
<LI>Should EDP be expanded into a symposium (full papers, proceedings)?
</UL>
</td>
</tr>
<tr>
<td ALIGN=3DCENTER COLSPAN=3D2 BGCOLOR=3D"#FFFFFF"><b><font
size=3D+1>12:0=
0-1:00 - Lunch and adjourn</font></b>
</td>
</tr>
</table>
</body>
</html>
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