Subject: FW: [vhdl-200x] Invitation to Shape VHDL 200x
From: Dennis Brophy (dennisb@model.com)
Date: Wed Feb 19 2003 - 06:55:16 PST
You may find proposed enhancements to VHDL to be of interest...
-----Original Message-----
From: Stephen Bailey [mailto:Stephen.Bailey@synopsys.com]
Sent: Thursday, January 16, 2003 9:48 PM
To: vhdl-200x@server.eda.org
Subject: [vhdl-200x] Invitation to Shape VHDL 200x
Greetings all,
And welcome to the vhdl-200x language revision effort.
As chair of the VHDL Analysis and Standardization Group (VASG) aka IEEE 1076
Working Group, I have the honor of inviting you to participate in a newly
organized effort to enhance and revise the VHDL language to better meet the
needs of designers today and the next several years. There are 3 important
notices in this email:
Why are you on the list (how to get off, if you don't want to be on the
list)
Invitation to our first meetings
Overview of likely activities
And, one action item: If you will be attending the technical meeting (see
below), in person, please "RSVP" so we can ensure we have adequate
facilities. If you will be attending via telecon/Webex, no RSVP is required
at this time.
1. Why am I getting this email? A few of you already know because you have
already been specifically asked to participate. However, to the best of my
knowledge, most of the people currently subscribed to this email list do not
realize that they have been nominated to participate. For those people, I
would like you to know that you were specifically nominated by a core group
of people who have been working the last month or two in organizing this
effort.
For those who have been nominated to participate, you of course do have the
choice of participating or not. If you do not wish to participate, please
unsubscribe from this list by sending the following email to
majordomo@eda.org <mailto:majordomo@eda.org> :
unsubscribe vhdl-200x <your-email-address-you-received-this-message-at>
If you can recommend someone else to participate, please do so.
If you are unsure which email address was used to subscribe you, send me an
email ( sbailey@synopsys.com <mailto:sbailey@synopsys.com> ) and I will let
you know.
For those of you who do wish to participate (and I do hope all of you decide
to participate), you may subscribe additional email addresses by sending
email to majordomo@eda.org <mailto:majordomo@eda.org> :
subscribe vhdl-200x <your-email-address>
Please note that posting privilege to this list is controlled. Only list
members may post.
It is important to note that the core group working on the initial
organizing activities have been working hard to identify people that are not
only likely to be active participants but also to ensure that we cover as
many important functional areas as possible:
- EDA Vendors
Simulation
Synthesis
Formal verification
- FPGA vendors
- End users
- Academia
2. Our first meetings will be held the same week as DVCon in San Jose, CA
(24 Feb 03).
Tues, 25 Feb @ 6pm:
We will be holding a public meeting at the DoubleTree Hotel in San Jose,
CA. (This is the site of the conference. We have made arrangements for the
room via Accellera and conference management.)
Purpose: To publicize the language enhancement project. Provide an
overview of the project and solicit information and participation.
Thurs, 27 Feb @ 9am:
Where: Mentor Graphics, San Jose, CA.
We will be holding our first technical meeting. Mentor has offered to
provide telecon and Webex access for this meeting to accomodate those who
cannot attend in person.
If you plan on attending in person, please let me know (
sbailey@synopsys.com <mailto:sbailey@synopsys.com> ) so we can ensure
adequate facilities.
If you plan on attending via Webex/telecon, we will be distributing
information at a later date on registering for the Webex access.
Our goal for this meeting is to have everything in place so that real work
can begin immediately afterwards.
3. Overview of Likely Activities
While there is nothing that is set in stone at this point in time, I don't
think I'm going out on a limb to sugges the following broad areas will
likely be explored:
- Productivity enhancements (both end-user productivity and tool
performance)
- Assertion-based verification
- Enhanced testbench/verification capabilities
- Higher abstraction capabilities and type system enhancements
- Interfaces and communication
Once again, welcome and I hope to see you at the technical meetings.
-----------------------------------------------------------------
Stephen Bailey
Staff Corporate Applications Engineer, VHDL Simulation
Synopsys Inc.
sbailey@synopsys.com <mailto:sbailey@synopsys.com>
303-775-1655 (voice/mobile)
650-584-4893 (corporate voice mail)
Read Verification Avenue:
http://www.synopsys.com/va <http://www.synopsys.com/va>
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