-- FILE NAME:        waves_utilities_.vhd
--
--                                   DISCLAIMER
--
--        This code is the sole property of the Institute for Technology
--        Development (ITD), Jackson, Mississippi, and is distributed for
--        the purpose of providing examples of VHDL models written to
--        modeling standards.  This code may not be used for commercial
--        purposes, and may not be redistributed without permission from
--        the Institute for Technology Development.  ITD assumes no 
--        responsibility for errors, omissions, uses made, or decisions
--        based on its use.  No warranties, expressed or implied, are given.
--
--        This is a modified IEEE WAVES package.  This package was modified
--        to handle the logic_mv state/strength value system used in the
--        models being tested.
--
--        ------------------------------------------------------------------

library STD_PACK ;
use STD_PACK.BASICDEFS.all ;
library EVENTS ;
use EVENTS.WAVES_PORT.all ;
use EVENTS.WAVES_INTERFACE.all ;
use EVENTS.WAVES_EVENTS.all;

package Waves_Utilities is

    type Comparison_Format is (
	Assign_To_Signal,
	Do_Assertion,
	Write_Comparison_To_File
    ) ;

    FUNCTION waves_to_logic_mv(waves_code: in CHARACTER) return logic_mv;

    FUNCTION logic_mv_to_waves(input: in logic_mv) return CHARACTER;

    FUNCTION Integer_to_logic_mv(input: Integer) return logic_mv;

    FUNCTION Waves_Port_to_Logic_Value (Input:  Waves_Port) return Logic_Value;
        -- retrieves the WAVES Logic_Value value associated with the value of
        -- a WAVES_PORT object (e.g., the element of Connect signal)

    procedure Check_Response (
    constant Which_One : in Positive ;
    signal Response : in logic_mv;
    signal Prediction : in Waves_Port ;
    signal Compare : in boolean ;
    constant How_To_Report : in Comparison_Format ;
    constant Assertion_Level : Severity_Level ;
    signal Match : out boolean
      ) ;

    procedure Signal_Monitor (
      Output_File_Name : in String ;
      signal Signals : in logic_mv_Vector
		-- Collection of all ports of DUT
		-- it has the same length as the number of pins in the DUT
		-- in the order specified in Test_Pins ;
      ) ;

end Waves_Utilities ;