-- -- -- DISCLAIMER -- -- This code is the sole property of the Institute for Technology -- Development (ITD), Jackson, Mississippi, and is distributed for -- the purpose of providing examples of VHDL models written to -- modeling standards. This code may not be used for commercial -- purposes, and may not be redistributed without permission from -- the Institute for Technology Development. ITD assumes no -- responsibility for errors, omissions, uses made, or decisions -- based on its use. No warranties, expressed or implied, are given. -- -- ------------------------------------------------------------------ -- FILE NAME: SN5438_.vhd -- PART NAME: SN5438 -- MANUFACTURER: TEXAS INSTRUMENTS -- REFERENCE: DATA SHEET - The 1988 TTL Data Book (2-155) -- PACKAGING: J SUFFIX (ceramic 14 pin DIP), or -- W SUFFIX (ceramic flat package) -- DESCRIPTION: -- -- The bipolar SSI SN5438 is a quad 2-input nand gate with open -- collector outputs. This model specifies propagation delays -- from a low '0' to a high impedance state 'Z' (tplz) and a -- high impedance state 'Z' to a low '0' (tpzl). This is NOT -- specified in the databook. The data book presumes a RC load -- to create a tplh and tphl specification. This does not reflect -- the stand-alone operation of the part. The modeling technique -- utilized uses the tplh and tphl times for the values of tplz -- and tpzl. The model writer realizes that this is not necessarily -- the best way to model the part, but is acceptable as a first order -- approximation. -- APPLICABLE FILES: -- SN5438_.vhd -- entity -- SN5438.vhd -- architecture -- SN5438.tim.vhd -- timing module -- SN5438_SIMFLAG_.vhd -- timing options declarations -- SN5438_SIMFLAG.vhd -- user-selected timing options -- waves_device_SN5438_.vhd -- test pins package declaration -- waves_device_SN5438.vhd -- test pins package body -- wgenerator_SN5438_.vhd -- WAVES test program package -- wgenerator_SN5438.vhd -- WAVES test program package body -- SN5438_TB_.vhd -- test bench entity -- SN5438_TB.vhd -- test bench architecture -- BASICDEFS_.vhd -- functional logic package declaration -- BASICDEFS.vhd -- functional logic package body -- waves_standard_.vhd -- basic WAVES definition package declaration -- waves_standard.vhd -- waves_standard package body -- waves_events_.vhd -- package which links events to logic values -- waves_events.vhd -- waves_events package body -- waves_port_.vhd -- defines type of interface of WAVES dataset -- waves_port.vhd -- waves_port package body -- waves_interface_.vhd -- defines functions for application of input -- values and for file input of test vectors -- waves_interface.vhd -- waves_interface package body -- waves_frames_.vhd -- links event values to pin codes -- waves_frames.vhd -- waves_frames package body -- waves_objects_.vhd -- defines functions that create slices -- waves_objects.vhd -- waves_objects package body -- waves_utilities_.vhd -- defines functions to check responses -- and to output port values to a file -- waves_utilities.vhd -- waves_utilities package body -- CONTACT: J. Scott Calhoun -- DEVELOPER: Institute for Technology Development -- VHDL Modeling Group -- 1 Research Blvd. -- Starkville, MS 39759 -- PHONE: (601)325-8365 -- DATE: 07-25-90 -- VERSION 1.1 -- REVISION HISTORY: (none) -- MODEL TYPE: Behavioral w/ timing. -- ANNOTATIONS: -- SUMMARY: library STD_PACK,WORK ; -- Defines utilized libraries use STD_PACK.BASICDEFS.all ; -- Defines types and subprograms use STD_PACK.TIME_FUNC.all ; -- Timing violation functions package use WORK.SN5438_TIMING.all ; -- SN5438 timing data package use WORK.SIMFLAG.all ; -- User-selectable timing options entity SN5438 is generic -- Switching characteristics ( tplz : time := 14 ns ; -- Prop delay low to high tpzl : time := 11 ns ; -- Prop delay high to low -- Wire delay parameters twd_P1 : time := 0 ns ; -- Wire delay on A1 twd_P2 : time := 0 ns ; -- Wire delay on B1 twd_P4 : time := 0 ns ; -- Wire delay on A2 twd_P5 : time := 0 ns ; -- Wire delay on B2 twd_P9 : time := 0 ns ; -- Wire delay on A3 twd_P10 : time := 0 ns ; -- Wire delay on B3 twd_P12 : time := 0 ns ; -- Wire delay on A4 twd_P13 : time := 0 ns ; -- Wire delay on B4 -- Output loading factor parameters tld_P3 : real := 1.0 ; -- Output loading factor for Y1 tld_P6 : real := 1.0 ; -- Output loading factor for Y2 tld_P8 : real := 1.0 ; -- Output loading factor for Y3 tld_P11 : real := 1.0 ; -- Output loading factor for Y4 ref : string := "U0" -- Component reference designator ) ; port -- Pin name/pin number assignments ( -- Output pins Y1 : out logic_mv_resolve := 'U' ; -- P3 Y2 : out logic_mv_resolve := 'U' ; -- P6 Y3 : out logic_mv_resolve := 'U' ; -- P8 Y4 : out logic_mv_resolve := 'U' ; -- P11 -- Input pins A1 : in logic_mv := 'U' ; -- P1 B1 : in logic_mv := 'U' ; -- P2 A2 : in logic_mv := 'U' ; -- P4 B2 : in logic_mv := 'U' ; -- P5 A3 : in logic_mv := 'U' ; -- P9 B3 : in logic_mv := 'U' ; -- P10 A4 : in logic_mv := 'U' ; -- P12 B4 : in logic_mv := 'U' -- P13 ) ; -- PIN MAPPING attribute PIN_NO : positive ; attribute PIN_NO of A1 : signal is 1 ; attribute PIN_NO of B1 : signal is 2 ; attribute PIN_NO of Y1 : signal is 3 ; attribute PIN_NO of A2 : signal is 4 ; attribute PIN_NO of B2 : signal is 5 ; attribute PIN_NO of Y2 : signal is 6 ; attribute PIN_NO of Y3 : signal is 8 ; attribute PIN_NO of A3 : signal is 9 ; attribute PIN_NO of B3 : signal is 10 ; attribute PIN_NO of Y4 : signal is 11 ; attribute PIN_NO of A4 : signal is 12 ; attribute PIN_NO of B4 : signal is 13 ; end SN5438 ;