-- -- -- DISCLAIMER -- -- This code is the sole property of the Institute for Technology -- Development (ITD), Jackson, Mississippi, and is distributed for -- the purpose of providing examples of VHDL models written to -- modeling standards. This code may not be used for commercial -- purposes, and may not be redistributed without permission from -- the Institute for Technology Development. ITD assumes no -- responsibility for errors, omissions, uses made, or decisions -- based on its use. No warranties, expressed or implied, are given. -- -- ------------------------------------------------------------------ -- FILE NAME: SN54LS112_.vhd -- PART NAME: SN54LS112 -- MANUFACTURER: FAIRCHILD SEMICONDUCTOR -- REFERENCE: DATA SHEET - Fairchild Semiconductor (4-153,4-154) -- PACKAGING: D SUFFIX (ceramic 16 pin DIP), or -- F SUFFIX (ceramic flat package) -- DESCRIPTION: -- -- The bipolar SSI SN54LS112 is a dual J-K negative-edge-triggered -- flip-flop with preset and clear. -- APPLICABLE FILES: -- SN54LS112_.vhd -- entity -- SN54LS112.vhd -- architecture -- SN54LS112.tim.vhd -- timing module -- SN54LS112_SIMFLAG_.vhd -- timing options declarations -- SN54LS112_SIMFLAG.vhd -- user-selected timing options -- waves_device_SN54LS112_.vhd -- test pins package declaration -- waves_device_SN54LS112.vhd -- test pins package body -- wgenerator_SN54LS112_.vhd -- WAVES test program package -- wgenerator_SN54LS112.vhd -- WAVES test program package body -- SN54LS112_TB_.vhd -- test bench entity -- SN54LS112_TB.vhd -- test bench architecture -- BASICDEFS_.vhd -- functional logic package declaration -- BASICDEFS.vhd -- functional logic package body -- waves_standard_.vhd -- basic WAVES definition package declaration -- waves_standard.vhd -- waves_standard package body -- waves_events_.vhd -- package which links events to logic values -- waves_events.vhd -- waves_events package body -- waves_port_.vhd -- defines type of interface of WAVES dataset -- waves_port.vhd -- waves_port package body -- waves_interface_.vhd -- defines functions for application of input -- values and for file input of test vectors -- waves_interface.vhd -- waves_interface package body -- waves_frames_.vhd -- links event values to pin codes -- waves_frames.vhd -- waves_frames package body -- waves_objects_.vhd -- defines functions that create slices -- waves_objects.vhd -- waves_objects package body -- waves_utilities_.vhd -- defines functions to check responses -- and to output port values to a file -- waves_utilities.vhd -- waves_utilities package body -- CONTACT: J. Scott Calhoun -- DEVELOPER: Institute for Technology Development -- VHDL Modeling Group -- 1 Research Blvd. -- Starkville, MS 39759 -- PHONE: (601)325-8365 -- DATE: 07-25-90 -- VERSION 1.1 -- REVISION HISTORY: (none) -- MODEL TYPE: Behavioral w/ timing. -- ANNOTATIONS: -- SUMMARY: library STD_PACK,WORK ; -- Defines utilized libraries use STD_PACK.BASICDEFS.all ; -- Defines types and subprograms use STD_PACK.TIME_FUNC.all ; -- Timing violation functions package use WORK.SN54LS112_TIMING.all ; -- SN54LS112 timing data package use WORK.SIMFLAG.all ; -- User-selectable timing options entity SN54LS112 is generic -- Recommended operating conditions ( tplh_clk_q : time := 9.600 ns; tplh_pr_q : time := 9.600 ns; tplh_clr_q : time := 9.600 ns; tphl_clk_q : time := 14.400 ns; tphl_pr_q : time := 14.400 ns; tphl_clr_q : time := 14.400 ns; tsu : time := 20.000 ns; th : time := 5.000 ns; tw_clk_lo : time := 15.000 ns; tw_clk_hi : time := 25.000 ns; tw_poc_lo : time := 25.000 ns; -- Wire delay parameters twd_P1 : time := 0 ns ; -- Wire delay on CLK1 twd_P2 : time := 0 ns ; -- Wire delay on K1 twd_P3 : time := 0 ns ; -- Wire delay on J1 twd_P4 : time := 0 ns ; -- Wire delay on PR1 twd_P10 : time := 0 ns ; -- Wire delay on PR2 twd_P11 : time := 0 ns ; -- Wire delay on J2 twd_P12 : time := 0 ns ; -- Wire delay on K2 twd_P13 : time := 0 ns ; -- Wire delay on CLK2 twd_P14 : time := 0 ns ; -- Wire delay on CLR2 twd_P15 : time := 0 ns ; -- Wire delay on CLR1 -- Output loading factor parameters tld_P5 : real := 1.0 ; -- Output loading factor for Q1 tld_P6 : real := 1.0 ; -- Output loading factor for QB1 tld_P7 : real := 1.0 ; -- Output loading factor for QB2 tld_P9 : real := 1.0 ; -- Output loading factor for Q2 ref : string := "U0" -- Component reference designator ) ; port -- Pin name/pin number assignments ( -- Output pins Q1 : out logic_mv := 'U' ; -- P5 QB1 : out logic_mv := 'U' ; -- P6 Q2 : out logic_mv := 'U' ; -- P9 QB2 : out logic_mv := 'U' ; -- P7 -- Input pins CLK1 : in logic_mv := 'U' ; -- P1 J1 : in logic_mv := 'U' ; -- P3 K1 : in logic_mv := 'U' ; -- P2 PR1 : in logic_mv := 'U' ; -- P4 CLR1 : in logic_mv := 'U' ; -- P15 CLK2 : in logic_mv := 'U' ; -- P13 J2 : in logic_mv := 'U' ; -- P11 K2 : in logic_mv := 'U' ; -- P12 PR2 : in logic_mv := 'U' ; -- P10 CLR2 : in logic_mv := 'U' -- P14 ) ; -- PIN MAPPING attribute PIN_NO : positive ; attribute PIN_NO of CLK1 : signal is 1 ; attribute PIN_NO of K1 : signal is 2 ; attribute PIN_NO of J1 : signal is 3 ; attribute PIN_NO of PR1 : signal is 4 ; attribute PIN_NO of Q1 : signal is 5 ; attribute PIN_NO of QB1 : signal is 6 ; attribute PIN_NO of QB2 : signal is 7 ; attribute PIN_NO of Q2 : signal is 9 ; attribute PIN_NO of PR2 : signal is 10 ; attribute PIN_NO of J2 : signal is 11 ; attribute PIN_NO of K2 : signal is 12 ; attribute PIN_NO of CLK2 : signal is 13 ; attribute PIN_NO of CLR2 : signal is 14 ; attribute PIN_NO of CLR1 : signal is 15 ; end SN54LS112 ;