-- -- -- DISCLAIMER -- -- This code is the sole property of the Institute for Technology -- Development (ITD), Jackson, Mississippi, and is distributed for -- the purpose of providing examples of VHDL models written to -- modeling standards. This code may not be used for commercial -- purposes, and may not be redistributed without permission from -- the Institute for Technology Development. ITD assumes no -- responsibility for errors, omissions, uses made, or decisions -- based on its use. No warranties, expressed or implied, are given. -- -- ------------------------------------------------------------------ -- FILENAME: SN54LS161.tim.vhd -- Description: timing module -- Created by Steve Turner 6/1/90 use WORK.SIMFLAG.all; package SN54LS161_TIMING is type modetype is (ERROR,CLR_CNTR,LD_CNTR,CNT,HOLD); type eflags is record x_out : boolean; no_time : boolean; end record; type messages is record tl : sim_options; option : time_options; mode : time_modes; end record; type times is record tplh_clk_rco : time; tplh_clk_qlh : time; tplh_clk_qll : time; tplh_en_rco : time; tphl_clk_rco : time; tphl_clk_qlh : time; tphl_clk_qll : time; tphl_en_rco : time; tphl_clr_q : time; tphl_clr_rco : time; --< not specified in data sheet. tw_clk : time; tw_clr : time; tsu_data : time; tsu_enable : time; tsu_load : time; th : time; end record; type sim_timing is record error_flags : eflags; prop_delays : times; sim_messages : messages; end record; type violate_flags is record clock : boolean ; clear : boolean ; ain_setup : boolean ; bin_setup : boolean ; cin_setup : boolean ; din_setup : boolean ; clr_setup : boolean ; enp_setup : boolean ; ent_setup : boolean ; load_setup : boolean ; ain_hold : boolean ; bin_hold : boolean ; cin_hold : boolean ; din_hold : boolean ; clr_hold : boolean ; enp_hold : boolean ; ent_hold : boolean ; load_hold : boolean ; end record ; type loads is record tld_QA : real; tld_QB : real; tld_QC : real; tld_QD : real; tld_RCO : real; end record; FUNCTION get_timing (gen_loads : IN loads; gen_times : IN times) RETURN sim_timing; end SN54LS161_TIMING; ---------------------------------------------------------------------- package body SN54LS161_TIMING is FUNCTION calc_curve ( X,C3,C2,C1,C0 : IN real ) RETURN real IS VARIABLE o : REAL; BEGIN o := C3*(X)**3 + C2*(X)**2 + C1*(X) + C0; RETURN o; END calc_curve; FUNCTION get_timing (gen_loads : IN loads; gen_times : IN times) RETURN sim_timing IS variable KU : real; variable KVLH,KTLH,deratingLH : real; variable KVHL,KTHL,deratingHL : real; variable mtime : sim_timing; begin -- Check for SIMFLAG options out-of-range if ( Ta < -55.0 or Ta > 125.0 ) then assert FALSE report "Temperature out of range" severity note; assert FALSE report "Check SIMFLAG.vhd file" severity error; elsif ( Vcc < 4.5 or Vcc > 5.5 ) then assert FALSE report "Voltage out of range" severity note; assert FALSE report "Check SIMFLAG.vhd file" severity error; elsif ( DERATE_FACTOR < 0.0 ) then assert FALSE report "Negative DERATE_FACTOR not allowed" severity note; assert FALSE report "Check SIMFLAG.vhd file" severity error; end if; if (FLAG_TYPE = GLOBAL) then -- Calculate derating factors KU := DERATE_FACTOR/100.0; KTLH := calc_curve(Ta,4.739047e-08,3.851426e-06,-1.259047e-04,1.000000e+00); KVLH := calc_curve(Vcc,0.000000,-1.999974e-03,-4.700023e-02,1.285001e+00); KTHL := calc_curve(Ta,-9.020953e-08,2.029714e-05,-1.496762e-03,1.026143e+00); KVHL := calc_curve(Vcc,0.000000,-1.999974e-03,-4.700023e-02,1.285001e+00); deratingLH := KVLH * KTLH * KU; deratingHL := KVHL * KTHL * KU; -- Select flags mtime.sim_messages.tl := SIM_OPTION; mtime.sim_messages.option := TIME_OPTION; mtime.sim_messages.mode := TIME_MODE; else -- Local Flags selected; use "normal" options mtime.sim_messages.tl := FULL_TIM; mtime.sim_messages.option := TYPICAL; mtime.sim_messages.mode := GENERIC_VALUES; end if; -- Set error flags if (mtime.sim_messages.tl = NO_TIM) then mtime.error_flags.x_out := FALSE; mtime.error_flags.no_time := TRUE; elsif (mtime.sim_messages.tl = ONLY_X) then mtime.error_flags.x_out := TRUE; mtime.error_flags.no_time := TRUE; elsif (mtime.sim_messages.tl = ONLY_DISPLAY) then mtime.error_flags.x_out := FALSE; mtime.error_flags.no_time := FALSE; elsif (mtime.sim_messages.tl = FULL_TIM) then mtime.error_flags.x_out := TRUE; mtime.error_flags.no_time := FALSE; end if; -- Select simulation timing delay values case mtime.sim_messages.mode is when GENERIC_VALUES => assert FALSE report "Using generic delay values" severity note ; mtime.prop_delays := gen_times; when TIMING => mtime.prop_delays.tw_clk := 25.000 ns; mtime.prop_delays.tw_clr := 20.000 ns; mtime.prop_delays.tsu_data := 20.000 ns; mtime.prop_delays.tsu_enable:= 20.000 ns; mtime.prop_delays.tsu_load := 20.000 ns; mtime.prop_delays.th := 5.000 ns; case mtime.sim_messages.option is when MINIMUM => mtime.prop_delays.tplh_clk_rco := 18.000 ns * deratingLH; mtime.prop_delays.tplh_clk_qlh := 11.700 ns * deratingLH; mtime.prop_delays.tplh_clk_qll := 11.700 ns * deratingLH; mtime.prop_delays.tplh_en_rco := 8.100 ns * deratingLH; mtime.prop_delays.tphl_clk_rco := 16.200 ns * deratingHL; mtime.prop_delays.tphl_clk_qlh := 16.200 ns * deratingHL; mtime.prop_delays.tphl_clk_qll := 16.200 ns * deratingHL; mtime.prop_delays.tphl_en_rco := 8.100 ns * deratingHL; mtime.prop_delays.tphl_clr_q := 18.000 ns * deratingHL; when TYPICAL => mtime.prop_delays.tplh_clk_rco := 20.000 ns * deratingLH; mtime.prop_delays.tplh_clk_qlh := 13.000 ns * deratingLH; mtime.prop_delays.tplh_clk_qll := 13.000 ns * deratingLH; mtime.prop_delays.tplh_en_rco := 9.000 ns * deratingLH; mtime.prop_delays.tphl_clk_rco := 18.000 ns * deratingHL; mtime.prop_delays.tphl_clk_qlh := 18.000 ns * deratingHL; mtime.prop_delays.tphl_clk_qll := 18.000 ns * deratingHL; mtime.prop_delays.tphl_en_rco := 9.000 ns * deratingHL; mtime.prop_delays.tphl_clr_q := 20.000 ns * deratingHL; when MAXIMUM => mtime.prop_delays.tplh_clk_rco := 35.000 ns * deratingLH; mtime.prop_delays.tplh_clk_qlh := 24.000 ns * deratingLH; mtime.prop_delays.tplh_clk_qll := 24.000 ns * deratingLH; mtime.prop_delays.tplh_en_rco := 14.000 ns * deratingLH; mtime.prop_delays.tphl_clk_rco := 35.000 ns * deratingHL; mtime.prop_delays.tphl_clk_qlh := 27.000 ns * deratingHL; mtime.prop_delays.tphl_clk_qll := 27.000 ns * deratingHL; mtime.prop_delays.tphl_en_rco := 14.000 ns * deratingHL; mtime.prop_delays.tphl_clr_q := 28.000 ns * deratingHL; end case; -- TIME_OPTION when ANNOTATED => assert FALSE report "Back annotation not available" severity warning ; assert FALSE report "Using generic delay values" severity note ; mtime.prop_delays := gen_times; end case; -- TIME_MODE ----------------------------------------------------------------------- -- tphl_clr_rco is not specified in the TTL Data Book. The logic diagram -- for the SN54LS161 indicates that the RCO output is the AND of QA,QB,QC, -- and QD. Therefore, the delay chosen for CLR to RCO (tphl_clr_rco) -- is the delay from CLR to Q (tphl_clr_q) plus the difference between -- CLK to RCO (tphl_clk_rco) and CLK to Q (tphl_clk_qll). ----------------------------------------------------------------------- mtime.prop_delays.tphl_clr_rco := mtime.prop_delays.tphl_clr_q + (mtime.prop_delays.tphl_clk_rco - mtime.prop_delays.tphl_clk_qll) ; RETURN(mtime); end get_timing; end SN54LS161_TIMING;