--
--
--                                   DISCLAIMER
--
--        This code is the sole property of the Institute for Technology
--        Development (ITD), Jackson, Mississippi, and is distributed for
--        the purpose of providing examples of VHDL models written to
--        modeling standards.  This code may not be used for commercial
--        purposes, and may not be redistributed without permission from
--        the Institute for Technology Development.  ITD assumes no 
--        responsibility for errors, omissions, uses made, or decisions
--        based on its use.  No warranties, expressed or implied, are given.
--
--        ------------------------------------------------------------------

architecture behavioral of SN54S02 is

-- ARCHITECTURE DECLARATIVE REGION

    constant generic_loads : loads := 
       (tld_P1,
        tld_P4,
        tld_P10,
        tld_P13) ;

    constant generic_times   : times := 
       (tplh_a_b_y,
        tphl_a_b_y) ;
        
    constant model_times   : sim_timing :=
        get_timing(generic_loads,generic_times) ;
        
    -- Local signal declarations

    signal ain1,ain2,ain3,ain4            : logic_mv := 'U' ;
    signal bin1,bin2,bin3,bin4            : logic_mv := 'U' ;
    signal yout1,yout2,yout3,yout4        : logic_mv := 'U' ;


-- ARCHITECTURE FUNCTIONAL REGION

begin

    -- assign pin values to internal signals after wire delay

    ain1 <= transport A1 after twd_P2 ;
    bin1 <= transport B1 after twd_P3 ;
    ain2 <= transport A2 after twd_P5 ;
    bin2 <= transport B2 after twd_P6 ;
    ain3 <= transport A3 after twd_P8 ;
    bin3 <= transport B3 after twd_P9 ;
    ain4 <= transport A4 after twd_P11 ;
    bin4 <= transport B4 after twd_P12 ;

    -- Assign internal values to output pins

    Y1 <= yout1 ;
    Y2 <= yout2 ;
    Y3 <= yout3 ;
    Y4 <= yout4 ;

-------------------------------------------------------------------------
NOR1 : process (ain1,bin1)

    variable temp : logic_mv ;

begin

    temp := ain1 NOR bin1 ;
    yout1 <= transport temp after tp_delay(temp,
             model_times.prop_delays.tplh_a_b_y,
             model_times.prop_delays.tphl_a_b_y);             

end process NOR1 ;

-------------------------------------------------------------------------
NOR2 : process (ain2,bin2)

    variable temp : logic_mv ;

begin

    temp := ain2 NOR bin2 ;
    yout2 <= transport temp after tp_delay(temp,
             model_times.prop_delays.tplh_a_b_y,
             model_times.prop_delays.tphl_a_b_y);             

end process NOR2 ;

-------------------------------------------------------------------------
NOR3 : process (ain3,bin3)

    variable temp : logic_mv ;

begin

    temp := ain3 NOR bin3 ;
    yout3 <= transport temp after tp_delay(temp,
             model_times.prop_delays.tplh_a_b_y,
             model_times.prop_delays.tphl_a_b_y);             

end process NOR3 ;

-------------------------------------------------------------------------
NOR4 : process (ain4,bin4)

    variable temp : logic_mv ;

begin

    temp := ain4 NOR bin4 ;
    yout4 <= transport temp after tp_delay(temp,
             model_times.prop_delays.tplh_a_b_y,
             model_times.prop_delays.tphl_a_b_y);             

end process NOR4 ;

end behavioral ;