--
--
--                                   DISCLAIMER
--
--        This code is the sole property of the Institute for Technology
--        Development (ITD), Jackson, Mississippi, and is distributed for
--        the purpose of providing examples of VHDL models written to
--        modeling standards.  This code may not be used for commercial
--        purposes, and may not be redistributed without permission from
--        the Institute for Technology Development.  ITD assumes no 
--        responsibility for errors, omissions, uses made, or decisions
--        based on its use.  No warranties, expressed or implied, are given.
--
--        ------------------------------------------------------------------

architecture behavioral of SN54S04 is

-- ARCHITECTURE DECLARATIVE REGION

    constant generic_loads : loads := 
       (tld_P2,
        tld_P4,
        tld_P6,
        tld_P8,
        tld_P10,
        tld_P12) ;

    constant generic_times   : times := 
       (tplh_a_y,
        tphl_a_y);

    constant model_times   : sim_timing :=
        get_timing(generic_loads,generic_times) ;

    -- Local signal declarations

    signal ain1,ain2,ain3,ain4,ain5,ain6   : logic_mv := 'U' ;
    signal yout1,yout2,yout3               : logic_mv := 'U' ;
    signal yout4,yout5,yout6               : logic_mv := 'U' ;

-- ARCHITECTURE FUNCTIONAL REGION

begin

    -- assign pin values to internal signals after wire delay
    -- 'H' is to be treated as a '1', and 'L' is to be treated as '0'

    ain1 <= transport Filter2(A1) after twd_P1 ;
    ain2 <= transport Filter2(A2) after twd_P3 ;
    ain3 <= transport Filter2(A3) after twd_P5 ;
    ain4 <= transport Filter2(A4) after twd_P9 ;
    ain5 <= transport Filter2(A5) after twd_P11 ;
    ain6 <= transport Filter2(A6) after twd_P13 ;

    -- Assign internal values to output pins

    Y1 <= yout1 ;
    Y2 <= yout2 ;
    Y3 <= yout3 ;
    Y4 <= yout4 ;
    Y5 <= yout5 ;
    Y6 <= yout6 ;

-------------------------------------------------------------------------
INV1 : process (ain1)

variable output_value : logic_mv;

begin

    output_value := not ain1;

    yout1 <= transport output_value after tp_delay(output_value,
             model_times.prop_delays.tplh_a_y ,
             model_times.prop_delays.tphl_a_y) ;

end process INV1 ;
-------------------------------------------------------------------------
INV2 : process (ain2)

variable output_value : logic_mv;

begin

    output_value := not ain2;

    yout2 <= transport output_value after tp_delay(output_value,
             model_times.prop_delays.tplh_a_y ,
             model_times.prop_delays.tphl_a_y) ;

end process INV2 ;
-------------------------------------------------------------------------
INV3 : process (ain3)

variable output_value : logic_mv;

begin

    output_value := not ain3;

    yout3 <= transport output_value after tp_delay(output_value,
             model_times.prop_delays.tplh_a_y ,
             model_times.prop_delays.tphl_a_y) ;

end process INV3 ;
-------------------------------------------------------------------------
INV4 : process (ain4)

variable output_value : logic_mv;

begin

    output_value := not ain4;

    yout4 <= transport output_value after tp_delay(output_value,
             model_times.prop_delays.tplh_a_y ,
             model_times.prop_delays.tphl_a_y) ;

end process INV4 ;
-------------------------------------------------------------------------
INV5 : process (ain5)

variable output_value : logic_mv;

begin

    output_value := not ain5;

    yout5 <= transport output_value after tp_delay(output_value,
             model_times.prop_delays.tplh_a_y ,
             model_times.prop_delays.tphl_a_y) ;

end process INV5 ;
-------------------------------------------------------------------------
INV6 : process (ain6)

variable output_value : logic_mv;

begin

    output_value := not ain6;

    yout6 <= transport output_value after tp_delay(output_value,
             model_times.prop_delays.tplh_a_y ,
             model_times.prop_delays.tphl_a_y) ;

end process INV6 ;

end behavioral ;