--
--
--                                   DISCLAIMER
--
--        This code is the sole property of the Institute for Technology
--        Development (ITD), Jackson, Mississippi, and is distributed for
--        the purpose of providing examples of VHDL models written to
--        modeling standards.  This code may not be used for commercial
--        purposes, and may not be redistributed without permission from
--        the Institute for Technology Development.  ITD assumes no 
--        responsibility for errors, omissions, uses made, or decisions
--        based on its use.  No warranties, expressed or implied, are given.
--
--        ------------------------------------------------------------------

-- FILENAME:    SN54S08.vhd
-- Description: behavioral architectural model

architecture behavioral of SN54S08 is

-- ARCHITECTURE DECLARATIVE REGION

    constant generic_loads : loads := 
       (tld_P3,
        tld_P6,
        tld_P8,
        tld_P11) ;

    constant generic_times   : times := 
       (tplh_a_b_y,
        tphl_a_b_y) ;
        
    constant model_times   : sim_timing :=
        get_timing(generic_loads,generic_times) ;
 
-- Local signal declarations

    signal ain1,ain2,ain3,ain4            : logic_mv := 'U' ;
    signal bin1,bin2,bin3,bin4            : logic_mv := 'U' ;
    signal yout1,yout2,yout3,yout4        : logic_mv := 'U' ;

-- ARCHITECTURE FUNCTIONAL REGION

begin

    -- assign pin values to internal signals after wire delay

    ain1 <= transport A1 after twd_P1 ;
    bin1 <= transport B1 after twd_P2 ;
    ain2 <= transport A2 after twd_P4 ;
    bin2 <= transport B2 after twd_P5 ;
    ain3 <= transport A3 after twd_P9 ;
    bin3 <= transport B3 after twd_P10 ;
    ain4 <= transport A4 after twd_P12 ;
    bin4 <= transport B4 after twd_P13 ;

    -- Assign internal values to output pins

    Y1 <= yout1 ;
    Y2 <= yout2 ;
    Y3 <= yout3 ;
    Y4 <= yout4 ;

-------------------------------------------------------------------------
AND1 : process (ain1,bin1)

    variable temp : logic_mv ;

begin

    temp := ain1 AND bin1 ;

    case temp is
    when '0' =>
        yout1 <= transport temp after model_times.prop_delays.tphl_a_b_y ;
    when '1' => 
        yout1 <= transport temp after model_times.prop_delays.tplh_a_b_y ;
    when others =>
        yout1 <= temp ;
    end case ;

end process AND1 ;
-------------------------------------------------------------------------

AND2 : process (ain2,bin2)

    variable temp : logic_mv ;

begin

    temp := ain2 AND bin2 ;

    case temp is
    when '0' =>
        yout2 <= transport temp after model_times.prop_delays.tphl_a_b_y ;
    when '1' => 
        yout2 <= transport temp after model_times.prop_delays.tplh_a_b_y ;
    when others =>
        yout2 <= temp ;
    end case ;

end process AND2 ;
-------------------------------------------------------------------------

AND3 : process (ain3,bin3)

    variable temp : logic_mv ;

begin

    temp := ain3 AND bin3 ;

    case temp is
    when '0' =>
        yout3 <= transport temp after model_times.prop_delays.tphl_a_b_y ;
    when '1' => 
        yout3 <= transport temp after model_times.prop_delays.tplh_a_b_y ;
    when others =>
        yout3 <= temp ;
    end case ;

end process AND3 ;
-------------------------------------------------------------------------

AND4 : process (ain4,bin4)

    variable temp : logic_mv ;

begin

    temp := ain4 AND bin4 ;

    case temp is
    when '0' =>
        yout4 <= transport temp after model_times.prop_delays.tphl_a_b_y ;
    when '1' => 
        yout4 <= transport temp after model_times.prop_delays.tplh_a_b_y ;
    when others =>
        yout4 <= temp ;
    end case ;

end process AND4 ;

end behavioral ;