--
--
--                                   DISCLAIMER
--
--        This code is the sole property of the Institute for Technology
--        Development (ITD), Jackson, Mississippi, and is distributed for
--        the purpose of providing examples of VHDL models written to
--        modeling standards.  This code may not be used for commercial
--        purposes, and may not be redistributed without permission from
--        the Institute for Technology Development.  ITD assumes no 
--        responsibility for errors, omissions, uses made, or decisions
--        based on its use.  No warranties, expressed or implied, are given.
--
--        ------------------------------------------------------------------

architecture behavioral of SN54S11 is

-- ARCHITECTURE DECLARATIVE REGION

-- Following signals added for incorporating timing

    constant generic_loads : loads := 
       (tld_P6,
        tld_P8,
        tld_P12) ;
        
    constant generic_times   : times := 
       (tplh_a_b_c_y,
        tphl_a_b_c_y) ;
        
    constant model_times   : sim_timing :=
        get_timing(generic_loads,generic_times) ;
 
    -- Local signal declarations

    signal ain1,ain2,ain3                 : logic_mv := 'U' ;
    signal bin1,bin2,bin3                 : logic_mv := 'U' ;
    signal cin1,cin2,cin3                 : logic_mv := 'U' ;
    signal yout1,yout2,yout3              : logic_mv := 'U' ;

-- ARCHITECTURE FUNCTIONAL REGION

begin

    -- assign pin values to internal signals after wire delay

    ain1 <= transport A1 after twd_P1 ;
    bin1 <= transport B1 after twd_P2 ;
    cin1 <= transport C1 after twd_P13 ;
    ain2 <= transport A2 after twd_P3 ;
    bin2 <= transport B2 after twd_P4 ;
    cin2 <= transport C2 after twd_P5 ;
    ain3 <= transport A3 after twd_P9 ;
    bin3 <= transport B3 after twd_P10 ;
    cin3 <= transport C3 after twd_P11 ;

    -- Assign internal values to output pins

    Y1 <= yout1 ;
    Y2 <= yout2 ;
    Y3 <= yout3 ;

-------------------------------------------------------------------------
AND3_1 : process (ain1,bin1,cin1)

    variable output_value : logic_mv ;

begin

    output_value := ain1 AND bin1 AND cin1 ;

    yout1 <= transport output_value after tp_delay(output_value,
             model_times.prop_delays.tplh_a_b_c_y,
             model_times.prop_delays.tphl_a_b_c_y) ;

end process AND3_1 ;
-------------------------------------------------------------------------
AND3_2 : process (ain2,bin2,cin2)

    variable output_value : logic_mv ;

begin

    output_value := ain2 AND bin2 AND cin2 ;

    yout2 <= transport output_value after tp_delay(output_value,
             model_times.prop_delays.tplh_a_b_c_y,
             model_times.prop_delays.tphl_a_b_c_y) ;

end process AND3_2 ;
-------------------------------------------------------------------------
AND3_3 : process (ain3,bin3,cin3)

    variable output_value : logic_mv ;

begin

    output_value := ain3 AND bin3 AND cin3 ;

    yout3 <= transport output_value after tp_delay(output_value,
             model_times.prop_delays.tplh_a_b_c_y,
             model_times.prop_delays.tphl_a_b_c_y) ;

end process AND3_3 ;

end behavioral ;