-- FILE NAME:        SN54S11_TB.vhd
--
--                                   DISCLAIMER
--
--        This code is the sole property of the Institute for Technology
--        Development (ITD), Jackson, Mississippi, and is distributed for
--        the purpose of providing examples of VHDL models written to
--        modeling standards.  This code may not be used for commercial
--        purposes, and may not be redistributed without permission from
--        the Institute for Technology Development.  ITD assumes no 
--        responsibility for errors, omissions, uses made, or decisions
--        based on its use.  No warranties, expressed or implied, are given.
--
--        ------------------------------------------------------------------
library DEVICE ;
use DEVICE.Waves_Device.all ;
use DEVICE.Waves_Objects.all ;
library WORK ;
use WORK.wgenerator_SN54S11.all ;
library EVENTS ;
use EVENTS.Waves_Utilities.all ;

architecture TEST_BENCH of SN54S11_TB is

    component DUT
      port (y1, y2, y3 : out logic_mv ;
            a1, b1, c1, a2, b2, c2, a3, b3, c3 : in  logic_mv ) ;
    end component ;

    for all : DUT use entity SN54S11.SN54S11 (BEHAVIORAL) ;

    -- Input and Output traffic of DUT
    signal T : logic_mv_vector(TEST_PIN_RANGE) ;

    -- Output file for results of signal monitor
    constant In_File_Name : string := "SN54S11_in.dat" ;
    constant Out_File_Name : string := "SN54S11_out.dat" ;

    signal Compare : boolean := TRUE ;
    constant How_To_Report : Comparison_Format := Do_Assertion ;
    constant Assertion_Level : Severity_Level := Warning ;
    signal SMatch : Waves_Match_List(TEST_PIN_RANGE) := (others => TRUE) ;

    -- Connection to WAVES dataset
    signal Connect : WAVES_PORT_LIST (TEST_PIN_RANGE) ;

    subtype COMPARE_PIN_RANGE is INTEGER range
        Test_Pins'Pos(TP_y1) + 1 to Test_Pins'Pos(TP_y3) + 1;

begin

    -- Call the waveform generator (i.e., the WAVES dataset)
    process begin
      SN54S11_TEST(Connect) ;
      wait ;
    end process ;

    -- Instantiate the Device under test

    Under_Test : DUT
    port map (
        T(Test_Pins'Pos(TP_y1) + 1),
        T(Test_Pins'Pos(TP_y2) + 1),
        T(Test_Pins'Pos(TP_y3) + 1),
        Integer_to_logic_mv(Connect(Test_Pins'Pos(TP_a1) + 1).DATA),
        Integer_to_logic_mv(Connect(Test_Pins'Pos(TP_b1) + 1).DATA),
        Integer_to_logic_mv(Connect(Test_Pins'Pos(TP_c1) + 1).DATA),
        Integer_to_logic_mv(Connect(Test_Pins'Pos(TP_a2) + 1).DATA),
        Integer_to_logic_mv(Connect(Test_Pins'Pos(TP_b2) + 1).DATA),
        Integer_to_logic_mv(Connect(Test_Pins'Pos(TP_c2) + 1).DATA),
        Integer_to_logic_mv(Connect(Test_Pins'Pos(TP_a3) + 1).DATA),
        Integer_to_logic_mv(Connect(Test_Pins'Pos(TP_b3) + 1).DATA),
        Integer_to_logic_mv(Connect(Test_Pins'Pos(TP_c3) + 1).DATA)
    ) ;

    -- Collect all signals (inputs and output of DUT) into signal T

    Collect_Inputs:
    for I in Test_Pins'Pos(TP_a1) + 1 to Test_Pins'Pos(TP_c3) + 1 generate
                T(I) <= Integer_to_logic_mv(Connect(I).DATA) ;
    end generate Collect_Inputs ;


    Signal_Traffic : Signal_Monitor(Out_File_Name, T) ;

    Gen_Comparator:
    for I in COMPARE_PIN_RANGE generate
      Comparator : Check_response(
        I,
        Response => T(I),
        Prediction => Connect(I),
        Compare => Compare,
        How_To_Report => How_To_Report,
        Assertion_Level => Assertion_Level,
        Match => SMatch(I) ) ;

      -- Integer_to_logic_mv(Convert the boolean signals of match into character values
      --  which take up less space in signal reports

    end generate Gen_Comparator ;

end TEST_BENCH ;