-- -- -- DISCLAIMER -- -- This code is the sole property of the Institute for Technology -- Development (ITD), Jackson, Mississippi, and is distributed for -- the purpose of providing examples of VHDL models written to -- modeling standards. This code may not be used for commercial -- purposes, and may not be redistributed without permission from -- the Institute for Technology Development. ITD assumes no -- responsibility for errors, omissions, uses made, or decisions -- based on its use. No warranties, expressed or implied, are given. -- --------------------------------------------------------------------------- -- Note: -- If enable and select inputs change in close sequence, timing -- complications may arise if an input event preempts the effects -- of a previous input event. In order to assign the correct -- propagation delay to an input signal, one must know what the -- future output will be after a particular propagation delay. -- For the SN54S138, one may predict the effect, if any, of an -- input event on each output. -- -- This SN54S138 model is based on the logic diagram on page 2-426 -- of the 1988 TTL Data Book. An internal signal exists for every -- unique path from an input to an output, and is assigned the -- corresponding input pin value after the appropriate propagation -- delay. Eight "zero-time" output processes (assert_yout0, etc.) -- respond to events on the internal signals. These output processes -- contain the actual decoding logic for the part. -- -- This approach provides a straightforward way to assign -- propagation delays, depending upon the number of logic levels and -- the effect an input has on an output. Although the logic diagram -- does not necessarily represent the actual implementation of the -- circuit, it does allow the model to accurately implement the -- timing behavior of the part. --------------------------------------------------------------------------- architecture behavioral of SN54S138 is -- ARCHITECTURE DECLARATIVE REGION constant generic_loads : loads := (tld_P15, tld_P14, tld_P13, tld_P12, tld_p11, tld_P10, tld_P9, tld_P7) ; constant generic_times : times := (tplh_bs2_y, tphl_bs2_y, tplh_bs3_y, tphl_bs3_y, tplh_en2_y, tphl_en2_y, tplh_en3_y, tphl_en3_y) ; constant model_times : sim_timing := get_timing(generic_loads,generic_times) ; -- Local signal declarations signal gin1,gin2a,gin2b : logic_mv := 'U' ; signal ain,bin,cin : logic_mv := 'U' ; signal yout0,yout1,yout2,yout3 : logic_mv := 'U' ; signal yout4,yout5,yout6,yout7 : logic_mv := 'U' ; signal gin1_y, gin2a_y, gin2b_y : logic_mv := 'U' ; signal ain_y0, bin_y0, cin_y0 : logic_mv := 'U' ; signal ain_y1, bin_y1, cin_y1 : logic_mv := 'U' ; signal ain_y2, bin_y2, cin_y2 : logic_mv := 'U' ; signal ain_y3, bin_y3, cin_y3 : logic_mv := 'U' ; signal ain_y4, bin_y4, cin_y4 : logic_mv := 'U' ; signal ain_y5, bin_y5, cin_y5 : logic_mv := 'U' ; signal ain_y6, bin_y6, cin_y6 : logic_mv := 'U' ; signal ain_y7, bin_y7, cin_y7 : logic_mv := 'U' ; -- ARCHITECTURE FUNCTIONAL REGION begin -- assign pin values to internal signals after wire delay -- 'H' is to be treated as a '1', and 'L' is to be treated as '0' ain <= transport Filter2(A) after twd_P1 ; bin <= transport Filter2(B) after twd_P2 ; cin <= transport Filter2(C) after twd_P3 ; gin1 <= transport Filter2(G1) after twd_P6 ; gin2a <= transport Filter2(G2A) after twd_P4 ; gin2b <= transport Filter2(G2B) after twd_P5 ; -- Assign internal values to output pins Y0 <= yout0 ; Y1 <= yout1 ; Y2 <= yout2 ; Y3 <= yout3 ; Y4 <= yout4 ; Y5 <= yout5 ; Y6 <= yout6 ; Y7 <= yout7 ; -- Check for invalid inputs on control input ports assert not (A'event and ((A = 'U') or (A = 'X') or (A = 'Z') or (A = 'W'))) report "{" & ref & "} " & enum_to_char(A) & " STATE ON A INPUT" severity warning ; assert not (B'event and ((B = 'U') or (B = 'X') or (B = 'Z') or (B = 'W'))) report "{" & ref & "} " & enum_to_char(B) & " STATE ON B INPUT" severity warning ; assert not (A'event and ((C = 'U') or (C = 'X') or (C = 'Z') or (C = 'W'))) report "{" & ref & "} " & enum_to_char(C) & " STATE ON C INPUT" severity warning ; assert not (G1'event and ((G1 = 'U') or (G1 = 'X') or (G1 = 'Z') or (G1 = 'W'))) report "{" & ref & "} " & enum_to_char(G1) & " STATE ON G1 INPUT" severity warning ; assert not (G2A'event and ((G2A = 'U') or (G2A = 'X') or (G2A = 'Z') or (G2A = 'W'))) report "{" & ref & "} " & enum_to_char(G2A) & " STATE ON G2A INPUT" severity warning ; assert not (G2B'event and ((G2B = 'U') or (G2B = 'X') or (G2B = 'Z') or (G2B = 'W'))) report "{" & ref & "} " & enum_to_char(G2B) & " STATE ON G2B INPUT" severity warning ; ------------------------------------------------------------------------------ gin_y : process (gin1, gin2a, gin2b) begin if (gin1'event) then gin1_y <= transport gin1 after tp_delay(not gin1, model_times.prop_delays.tplh_en3_y, model_times.prop_delays.tphl_en3_y) ; end if ; if (gin2a'event) then gin2a_y <= transport gin2a after tp_delay(gin2a, model_times.prop_delays.tplh_en2_y, model_times.prop_delays.tphl_en2_y ); end if ; if (gin2b'event) then gin2b_y <= transport gin2b after tp_delay(gin2b, model_times.prop_delays.tplh_en2_y, model_times.prop_delays.tphl_en2_y) ; end if ; end process gin_y ; ------------------------------------------------------------------------------ in_y0 : process (ain, bin, cin) begin if (ain'event) then ain_y0 <= transport ain after tp_delay(ain, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; if (bin'event) then bin_y0 <= transport bin after tp_delay(bin, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; if (cin'event) then cin_y0 <= transport cin after tp_delay(cin, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; end process in_y0 ; ------------------------------------------------------------------------------ in_y1 : process (ain, bin, cin) begin if (ain'event) then ain_y1 <= transport ain after tp_delay(not ain, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; if (bin'event) then bin_y1 <= transport bin after tp_delay(bin, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; if (cin'event) then cin_y1 <= transport cin after tp_delay(cin, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; end process in_y1 ; ------------------------------------------------------------------------------ in_y2 : process (ain, bin, cin) begin if (ain'event) then ain_y2 <= transport ain after tp_delay(ain, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; if (bin'event) then bin_y2 <= transport bin after tp_delay(not bin, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; if (cin'event) then cin_y2 <= transport cin after tp_delay(cin, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; end process in_y2 ; ------------------------------------------------------------------------------ in_y3 : process (ain, bin, cin) begin if (ain'event) then ain_y3 <= transport ain after tp_delay(not ain, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; if (bin'event) then bin_y3 <= transport bin after tp_delay(not bin, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; if (cin'event) then cin_y3 <= transport cin after tp_delay(cin, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; end process in_y3 ; ------------------------------------------------------------------------------ in_y4 : process (ain, bin, cin) begin if (ain'event) then ain_y4 <= transport ain after tp_delay(ain, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; if (bin'event) then bin_y4 <= transport bin after tp_delay(bin, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; if (cin'event) then cin_y4 <= transport cin after tp_delay(not cin, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; end process in_y4 ; ------------------------------------------------------------------------------ in_y5 : process (ain, bin, cin) begin if (ain'event) then ain_y5 <= transport ain after tp_delay(not ain, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; if (bin'event) then bin_y5 <= transport bin after tp_delay(bin, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; if (cin'event) then cin_y5 <= transport cin after tp_delay(not cin, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; end process in_y5 ; ------------------------------------------------------------------------------ in_y6 : process (ain, bin, cin) begin if (ain'event) then ain_y6 <= transport ain after tp_delay(ain, model_times.prop_delays.tplh_bs2_y, model_times.prop_delays.tphl_bs2_y); end if ; if (bin'event) then bin_y6 <= transport bin after tp_delay(not bin, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; if (cin'event) then cin_y6 <= transport cin after tp_delay(not cin, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; end process in_y6 ; ------------------------------------------------------------------------------ in_y7 : process (ain, bin, cin) begin if (ain'event) then ain_y7 <= transport ain after tp_delay(not ain, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; if (bin'event) then bin_y7 <= transport bin after tp_delay(not bin, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; if (cin'event) then cin_y7 <= transport cin after tp_delay(not cin, model_times.prop_delays.tplh_bs3_y, model_times.prop_delays.tphl_bs3_y); end if ; end process in_y7 ; ------------------------------------------------------------------------------ assertyout0 : process (gin1_y, gin2a_y, gin2b_y, ain_y0, bin_y0, cin_y0) variable enablev : logic_mv ; begin enablev := gin1_y and not gin2a_y and not gin2b_y ; yout0 <= not (enablev and not ain_y0 and not bin_y0 and not cin_y0) ; end process assertyout0 ; ------------------------------------------------------------------------------ assertyout1 : process (gin1_y, gin2a_y, gin2b_y, ain_y1, bin_y1, cin_y1) variable enablev : logic_mv ; begin enablev := gin1_y and not gin2a_y and not gin2b_y ; yout1 <= not (enablev and ain_y1 and not bin_y1 and not cin_y1) ; end process assertyout1 ; ------------------------------------------------------------------------------ assertyout2 : process (gin1_y, gin2a_y, gin2b_y, ain_y2, bin_y2, cin_y2) variable enablev : logic_mv ; begin enablev := gin1_y and not gin2a_y and not gin2b_y ; yout2 <= not (enablev and not ain_y2 and bin_y2 and not cin_y2) ; end process assertyout2 ; ------------------------------------------------------------------------------ assertyout3 : process (gin1_y, gin2a_y, gin2b_y, ain_y3, bin_y3, cin_y3) variable enablev : logic_mv ; begin enablev := gin1_y and not gin2a_y and not gin2b_y ; yout3 <= not (enablev and ain_y3 and bin_y3 and not cin_y3) ; end process assertyout3 ; ------------------------------------------------------------------------------ assertyout4 : process (gin1_y, gin2a_y, gin2b_y, ain_y4, bin_y4, cin_y4) variable enablev : logic_mv ; begin enablev := gin1_y and not gin2a_y and not gin2b_y ; yout4 <= not (enablev and not ain_y4 and not bin_y4 and cin_y4) ; end process assertyout4 ; ------------------------------------------------------------------------------ assertyout5 : process (gin1_y, gin2a_y, gin2b_y, ain_y5, bin_y5, cin_y5) variable enablev : logic_mv ; begin enablev := gin1_y and not gin2a_y and not gin2b_y ; yout5 <= not (enablev and ain_y5 and not bin_y5 and cin_y5) ; end process assertyout5 ; ------------------------------------------------------------------------------ assertyout6 : process (gin1_y, gin2a_y, gin2b_y, ain_y6, bin_y6, cin_y6) variable enablev : logic_mv ; begin enablev := gin1_y and not gin2a_y and not gin2b_y ; yout6 <= not (enablev and not ain_y6 and bin_y6 and cin_y6) ; end process assertyout6 ; ------------------------------------------------------------------------------ assertyout7 : process (gin1_y, gin2a_y, gin2b_y, ain_y7, bin_y7, cin_y7) variable enablev : logic_mv ; begin enablev := gin1_y and not gin2a_y and not gin2b_y ; yout7 <= not (enablev and ain_y7 and bin_y7 and cin_y7) ; end process assertyout7 ; ------------------------------------------------------------------------------ end behavioral ;