--
--
--                                   DISCLAIMER
--
--        This code is the sole property of the Institute for Technology
--        Development (ITD), Jackson, Mississippi, and is distributed for
--        the purpose of providing examples of VHDL models written to
--        modeling standards.  This code may not be used for commercial
--        purposes, and may not be redistributed without permission from
--        the Institute for Technology Development.  ITD assumes no 
--        responsibility for errors, omissions, uses made, or decisions
--        based on its use.  No warranties, expressed or implied, are given.
--
--        ------------------------------------------------------------------

architecture behavioral of SN54S140 is

-- ARCHITECTURE DECLARATIVE REGION

-- Following signals added for incorporating timing

    constant generic_loads : loads := 
       (tld_P6,
        tld_P8) ;

    constant generic_times   : times := 
       (tplh_a_b_c_d_y,
        tphl_a_b_c_d_y) ;
        
    constant model_times   : sim_timing :=
        get_timing(generic_loads,generic_times) ;        

-- Local signal declarations

    signal ain1,ain2                      : logic_mv := 'U' ;
    signal bin1,bin2                      : logic_mv := 'U' ;
    signal cin1,cin2                      : logic_mv := 'U' ;
    signal din1,din2                      : logic_mv := 'U' ;
    signal yout1,yout2                    : logic_mv := 'U' ;

-- ARCHITECTURE FUNCTIONAL REGION

begin

    -- assign pin values to internal signals after wire delay

    ain1 <= transport A1 after twd_P1 ;
    bin1 <= transport B1 after twd_P2 ;
    cin1 <= transport C1 after twd_P4 ;
    din1 <= transport D1 after twd_P5 ;
    ain2 <= transport A2 after twd_P9 ;
    bin2 <= transport B2 after twd_P10 ;
    cin2 <= transport C2 after twd_P12 ;
    din2 <= transport D2 after twd_P13 ;

    -- Assign internal values to output pins

    Y1 <= yout1 ;
    Y2 <= yout2 ;

-------------------------------------------------------------------------
NAND4_1 : process (ain1,bin1,cin1,din1)

    variable temp : logic_mv ;

begin

    temp := NOT(ain1 AND bin1 AND cin1 AND din1) ;

    case temp is
    when '0' =>
        yout1 <= transport temp after model_times.prop_delays.tphl_a_b_c_d_y ;
    when '1' => 
        yout1 <= transport temp after model_times.prop_delays.tplh_a_b_c_d_y ;
    when others =>
        yout1 <= temp ;
    end case ;

end process NAND4_1 ;
-------------------------------------------------------------------------
NAND4_2 : process (ain2,bin2,cin2,din2)

    variable temp : logic_mv ;

begin

    temp := NOT(ain2 AND bin2 AND cin2 AND din2) ;

    case temp is
    when '0' =>
        yout2 <= transport temp after model_times.prop_delays.tphl_a_b_c_d_y ;
    when '1' => 
        yout2 <= transport temp after model_times.prop_delays.tplh_a_b_c_d_y ;
    when others =>
        yout2 <= temp ;
    end case ;

end process NAND4_2 ;

end behavioral ;