-- -- -- DISCLAIMER -- -- This code is the sole property of the Institute for Technology -- Development (ITD), Jackson, Mississippi, and is distributed for -- the purpose of providing examples of VHDL models written to -- modeling standards. This code may not be used for commercial -- purposes, and may not be redistributed without permission from -- the Institute for Technology Development. ITD assumes no -- responsibility for errors, omissions, uses made, or decisions -- based on its use. No warranties, expressed or implied, are given. -- -- ------------------------------------------------------------------ -- FILE NAME: SN54S251_.vhd -- PART NAME: SN54S251 -- MANUFACTURER: TEXAS INSTRUMENTS -- REFERENCE: DATA SHEET - The 1988 TTL Data Book (2-718) -- PACKAGING: J SUFFIX (ceramic 16 pin DIP), or -- W SUFFIX (ceramic flat package) -- DESCRIPTION: -- -- The bipolar SSI SN54S251 is a bipolar 8 to 1 multiplexer -- with 3-state outputs. This circuit specifies the output -- state based two separate algorithms. The first -- determines the propagation delays assigned -- to a particular output based on input transitions. -- Some special calculations must be made if more than -- one control input change in a short period of time. The -- second determines the transitions (0->1 or 1->0) the -- outputs will make for a given input state. -- APPLICABLE FILES: -- SN54S251_.vhd -- entity -- SN54S251.vhd -- architecture -- SN54S251.tim.vhd -- timing module -- SN54S251_SIMFLAG_.vhd -- timing options declarations -- SN54S251_SIMFLAG.vhd -- user-selected timing options -- waves_device_SN54S251_.vhd -- test pins package declaration -- waves_device_SN54S251.vhd -- test pins package body -- wgenerator_SN54S251_.vhd -- WAVES test program package -- wgenerator_SN54S251.vhd -- WAVES test program package body -- SN54S251_TB_.vhd -- test bench entity -- SN54S251_TB.vhd -- test bench architecture -- BASICDEFS_.vhd -- functional logic package declaration -- BASICDEFS.vhd -- functional logic package body -- waves_standard_.vhd -- basic WAVES definition package declaration -- waves_standard.vhd -- waves_standard package body -- waves_events_.vhd -- package which links events to logic values -- waves_events.vhd -- waves_events package body -- waves_port_.vhd -- defines type of interface of WAVES dataset -- waves_port.vhd -- waves_port package body -- waves_interface_.vhd -- defines functions for application of input -- values and for file input of test vectors -- waves_interface.vhd -- waves_interface package body -- waves_frames_.vhd -- links event values to pin codes -- waves_frames.vhd -- waves_frames package body -- waves_objects_.vhd -- defines functions that create slices -- waves_objects.vhd -- waves_objects package body -- waves_utilities_.vhd -- defines functions to check responses -- and to output port values to a file -- waves_utilities.vhd -- waves_utilities package body -- CONTACT: J. Scott Calhoun -- DEVELOPER: Institute for Technology Development -- VHDL Modeling Group -- 1 Research Blvd. -- Starkville, MS 39759 -- PHONE: (601)325-8365 -- DATE: 07-25-90 -- VERSION 1.1 -- REVISION HISTORY: (none) -- MODEL TYPE: Behavioral w/ timing. -- ANNOTATIONS: -- SUMMARY: library STD_PACK,WORK ; -- Defines utilized libraries use STD_PACK.BASICDEFS.all ; -- Defines types and subprograms use STD_PACK.TIME_FUNC.all ; -- Timing violation functions package use WORK.SN54S251_TIMING.all ; -- SN54S251 timing data package use WORK.SIMFLAG.all ; -- User-selectable timing options entity SN54S251 is generic -- Switching characteristics ( tplh_bs_y : time := 29 ns ; -- Prop delay low to high binary -- select to Y (4 level) tphl_bs_y : time := 28 ns ; -- Prop delay high to low binary -- select to Y (4 level) tplh_bs_w : time := 20 ns ; -- Prop delay low to high binary -- select to W (3 level) tphl_bs_w : time := 21 ns ; -- Prop delay high to low binary -- select to W (3 level) tplh_d_y : time := 17 ns ; -- Prop delay low to high data to Y tphl_d_y : time := 18 ns ; -- Prop delay high to low data to Y tplh_d_w : time := 10 ns ; -- Prop delay low to high data to W tphl_d_w : time := 9 ns ; -- Prop delay high to low data to W tpzh_g_y : time := 17 ns ; -- Prop delay enable to high Y tpzl_g_y : time := 26 ns ; -- Prop delay enable to low Y tpzh_g_w : time := 17 ns ; -- Prop delay enable to high W tpzl_g_w : time := 24 ns ; -- Prop delay enable to low W tphz_g_y : time := 5.5 ns ; -- Prop delay high to disable Y tplz_g_y : time := 9 ns ; -- Prop delay low to disable Y tphz_g_w : time := 5.5 ns ; -- Prop delay high to disable W tplz_g_w : time := 9 ns ; -- Prop delay low to disable W -- Wire delay parameters twd_P7 : time := 0 ns ; -- Wire delay on STR twd_P11 : time := 0 ns ; -- Wire delay on A twd_P10 : time := 0 ns ; -- Wire delay on B twd_P9 : time := 0 ns ; -- Wire delay on C twd_P4 : time := 0 ns ; -- Wire delay on D0 twd_P3 : time := 0 ns ; -- Wire delay on D1 twd_P2 : time := 0 ns ; -- Wire delay on D2 twd_P1 : time := 0 ns ; -- Wire delay on D3 twd_P15 : time := 0 ns ; -- Wire delay on D4 twd_P14 : time := 0 ns ; -- Wire delay on D5 twd_P13 : time := 0 ns ; -- Wire delay on D6 twd_P12 : time := 0 ns ; -- Wire delay on D7 -- Output loading factor parameters tld_P5 : real := 1.0 ; -- Output loading factor for Y tld_P6 : real := 1.0 ; -- Output loading factor for W ref : string := "U0" -- Component reference designator ) ; port -- Pin name/pin number assignments ( -- Output pins Y : out logic_mv_resolve := 'U' ; -- P5 W : out logic_mv_resolve := 'U' ; -- P6 -- Input pins STR : in logic_mv := 'U' ; -- P7 A : in logic_mv := 'U' ; -- P11 B : in logic_mv := 'U' ; -- P10 C : in logic_mv := 'U' ; -- P9 D0 : in logic_mv := 'U' ; -- P4 D1 : in logic_mv := 'U' ; -- P3 D2 : in logic_mv := 'U' ; -- P2 D3 : in logic_mv := 'U' ; -- P1 D4 : in logic_mv := 'U' ; -- P15 D5 : in logic_mv := 'U' ; -- P14 D6 : in logic_mv := 'U' ; -- P13 D7 : in logic_mv := 'U' -- P12 ) ; -- PIN MAPPING attribute PIN_NO : positive ; attribute PIN_NO of D3 : signal is 1 ; attribute PIN_NO of D2 : signal is 2 ; attribute PIN_NO of D1 : signal is 3 ; attribute PIN_NO of D0 : signal is 4 ; attribute PIN_NO of Y : signal is 5 ; attribute PIN_NO of W : signal is 6 ; attribute PIN_NO of STR : signal is 7 ; attribute PIN_NO of C : signal is 9 ; attribute PIN_NO of B : signal is 10 ; attribute PIN_NO of A : signal is 11 ; attribute PIN_NO of D7 : signal is 12 ; attribute PIN_NO of D6 : signal is 13 ; attribute PIN_NO of D5 : signal is 14 ; attribute PIN_NO of D4 : signal is 15 ; end SN54S251 ;