--
--
--                                   DISCLAIMER
--
--        This code is the sole property of the Institute for Technology
--        Development (ITD), Jackson, Mississippi, and is distributed for
--        the purpose of providing examples of VHDL models written to
--        modeling standards.  This code may not be used for commercial
--        purposes, and may not be redistributed without permission from
--        the Institute for Technology Development.  ITD assumes no 
--        responsibility for errors, omissions, uses made, or decisions
--        based on its use.  No warranties, expressed or implied, are given.
--
--        ------------------------------------------------------------------

architecture behavioral of SN54S280 is

-- ARCHITECTURE DECLARATIVE REGION

    constant generic_loads : loads := 
       (tld_P5,
        tld_P6) ;
        
    constant generic_times   : times := 
       (tplh_even,
        tphl_even,
        tplh_odd,
        tphl_odd) ;
        
    constant model_times   : sim_timing :=
        get_timing(generic_loads,generic_times) ;        

    -- Local signal declarations

    signal ain,bin,cin,din                : logic_mv := 'U' ;
    signal ein,fin,gin,hin,iin            : logic_mv := 'U' ;
    signal evenout,oddout                 : logic_mv := 'U' ;

-- ARCHITECTURE FUNCTIONAL REGION

begin

    -- assign pin values to internal signals after wire delay

    ain   <= transport A after twd_P8 ;
    bin   <= transport B after twd_P9 ;
    cin   <= transport C after twd_P10 ;
    din   <= transport D after twd_P11 ;
    ein   <= transport E after twd_P12 ;
    fin   <= transport F after twd_P13 ;
    gin   <= transport G after twd_P1 ;
    hin   <= transport H after twd_P2 ;
    iin   <= transport I after twd_P4 ;

    -- Assign input values to output pins

    EVEN <= evenout ;
    ODD  <= oddout ;

-------------------------------------------------------------------------
PARITY : process (ain,bin,cin,din,ein,fin,gin,hin,iin)

variable par : logic_mv ;

begin

    par := (ain xor bin xor cin xor din xor ein xor 
            fin xor gin xor hin xor iin) ;

    if (par = '1') then
        oddout  <= transport '1' after model_times.prop_delays.tplh_d_odd ;
        evenout <= transport '0' after model_times.prop_delays.tphl_d_even ;
    elsif (par = '0') then   
        oddout  <= transport '0' after model_times.prop_delays.tphl_d_odd ;
        evenout <= transport '1' after model_times.prop_delays.tplh_d_even ;
    elsif (ain = 'U' or bin = 'U' or cin = 'U' or din = 'U' or ein = 'U' or 
           fin = 'U' or gin = 'U' or hin = 'U' or iin = 'U') then
        oddout  <= 'U' ;
        evenout <= 'U' ;
    else
        oddout  <= 'X' ;
        evenout <= 'X' ;
    end if ;

end process PARITY ;

end behavioral ;