--
--
--                                   DISCLAIMER
--
--        This code is the sole property of the Institute for Technology
--        Development (ITD), Jackson, Mississippi, and is distributed for
--        the purpose of providing examples of VHDL models written to
--        modeling standards.  This code may not be used for commercial
--        purposes, and may not be redistributed without permission from
--        the Institute for Technology Development.  ITD assumes no 
--        responsibility for errors, omissions, uses made, or decisions
--        based on its use.  No warranties, expressed or implied, are given.
--
--        ------------------------------------------------------------------

-- FILE NAME:              SN54S280_.vhd

-- PART NAME:              SN54S280
-- MANUFACTURER:           TEXAS INSTRUMENTS
-- REFERENCE:              DATA SHEET - The 1988 TTL Data Book (2-778)
-- PACKAGING:              J SUFFIX (ceramic 14 pin DIP), or
--                         W SUFFIX (ceramic flat package)
-- DESCRIPTION:             
--
-- The bipolar SSI SN54S280 is a 9-bit even/odd parity generator/checker

-- APPLICABLE FILES:  

-- SN54S280_.vhd                -- entity
-- SN54S280.vhd                 -- architecture
-- SN54S280.tim.vhd             -- timing module
-- SN54S280_SIMFLAG_.vhd        -- timing options declarations
-- SN54S280_SIMFLAG.vhd         -- user-selected timing options
-- waves_device_SN54S280_.vhd   -- test pins package declaration
-- waves_device_SN54S280.vhd    -- test pins package body
-- wgenerator_SN54S280_.vhd     -- WAVES test program package
-- wgenerator_SN54S280.vhd      -- WAVES test program package body
-- SN54S280_TB_.vhd             -- test bench entity
-- SN54S280_TB.vhd              -- test bench architecture
-- BASICDEFS_.vhd             -- functional logic package declaration
-- BASICDEFS.vhd              -- functional logic package body
-- waves_standard_.vhd        -- basic WAVES definition package declaration
-- waves_standard.vhd         -- waves_standard package body
-- waves_events_.vhd          -- package which links events to logic values
-- waves_events.vhd           -- waves_events package body
-- waves_port_.vhd            -- defines type of interface of WAVES dataset
-- waves_port.vhd             -- waves_port package body
-- waves_interface_.vhd       -- defines functions for application of input
--                               values and for file input of test vectors
-- waves_interface.vhd        -- waves_interface package body
-- waves_frames_.vhd          -- links event values to pin codes
-- waves_frames.vhd           -- waves_frames package body
-- waves_objects_.vhd         -- defines functions that create slices
-- waves_objects.vhd          -- waves_objects package body
-- waves_utilities_.vhd       -- defines functions to check responses
--                               and to output port values to a file
-- waves_utilities.vhd        -- waves_utilities package body
 
 
-- CONTACT:                J. Scott Calhoun
-- DEVELOPER:              Institute for Technology Development
--                         VHDL Modeling Group
--                         1 Research Blvd.
--                         Starkville, MS 39759
-- PHONE:                  (601)325-8365
-- DATE:                   07-25-90
-- VERSION                 1.1
-- REVISION HISTORY:       (none)
-- MODEL TYPE:             Behavioral w/ timing.

-- ANNOTATIONS:           

-- SUMMARY:

library STD_PACK,WORK ;              -- Defines utilized libraries
use STD_PACK.BASICDEFS.all ;         -- Defines types and subprograms
use STD_PACK.TIME_FUNC.all ;         -- Timing violation functions package
use WORK.SN54S280_TIMING.all ;       -- SN54S280 timing data package
use WORK.SIMFLAG.all ;               -- User-selectable timing options

entity SN54S280 is

    generic                          -- Switching characteristics         
    (
    tplh_even     : time := 14 ns ;  -- Prop delay low to high even
    tphl_even     : time := 11.5 ns ;-- Prop delay high to low even
    tplh_odd      : time := 14 ns ;  -- Prop delay low to high odd
    tphl_odd      : time := 11.5 ns ;-- Prop delay high to low odd

                                     -- Wire delay parameters

    twd_P8       : time :=  0 ns ;   -- Wire delay on A
    twd_P9       : time :=  0 ns ;   -- Wire delay on B
    twd_P10      : time :=  0 ns ;   -- Wire delay on C
    twd_P11      : time :=  0 ns ;   -- Wire delay on D
    twd_P12      : time :=  0 ns ;   -- Wire delay on E
    twd_P13      : time :=  0 ns ;   -- Wire delay on F
    twd_P1       : time :=  0 ns ;   -- Wire delay on G
    twd_P2       : time :=  0 ns ;   -- Wire delay on H
    twd_P4       : time :=  0 ns ;   -- Wire delay on I

                                     -- Output loading factor parameters

    tld_P5       : real :=  1.0 ;    -- Output loading factor for Y
    tld_P6       : real :=  1.0 ;    -- Output loading factor for W

    ref          : string := "U0"    -- Component reference designator

    ) ;

    port                             -- Pin name/pin number assignments
    (
                                     -- Output pins

     EVEN      : out logic_mv := 'U' ; -- P5
     ODD       : out logic_mv := 'U' ; -- P6

                                     -- Input pins
  
     A         : in logic_mv := 'U' ;  -- P8
     B         : in logic_mv := 'U' ;  -- P9
     C         : in logic_mv := 'U' ;  -- P10
     D         : in logic_mv := 'U' ;  -- P11
     E         : in logic_mv := 'U' ;  -- P12
     F         : in logic_mv := 'U' ;  -- P13
     G         : in logic_mv := 'U' ;  -- P1
     H         : in logic_mv := 'U' ;  -- P2
     I         : in logic_mv := 'U'    -- P4
     ) ;

                                     -- PIN MAPPING

     attribute PIN_NO         : positive ;
     attribute PIN_NO of G    : signal is 1 ;
     attribute PIN_NO of H    : signal is 2 ;
     attribute PIN_NO of I    : signal is 4 ;
     attribute PIN_NO of EVEN : signal is 5 ;
     attribute PIN_NO of ODD  : signal is 6 ;
     attribute PIN_NO of A    : signal is 8 ;
     attribute PIN_NO of B    : signal is 9 ;
     attribute PIN_NO of C    : signal is 10 ;
     attribute PIN_NO of D    : signal is 11 ;
     attribute PIN_NO of E    : signal is 12 ;
     attribute PIN_NO of F    : signal is 13 ;
 
end SN54S280 ;