Fall 1989 VHDL Users' Group Meeting VHDL in the Design Environment Invitation and Agenda 22-25 October 1989 Sheraton @ Redondo Beach Redondo Beach, CA Sponsored by the VHDL Users' Group In Cooperation with the Electronic Industries Association -------------------------------------------------------------------------- Introduction VHDL, a hardware design and description language, was approved as an IEEE Standard (1076-1987) on December 10, 1987. VHDL documentation is now required for all digital ASIC's developed under DoD contract (see Mil Std 454, Req 64). A data item description has been established which defines the language documentation requirements for all digital electronic designs. It is anticipated that VHDL will become a standard deliverable for all DoD development and procurement programs. The need to link CAD tools in the design process is driving commercial adoption of VHDL. Commercial VHDL tools are already in use or being developed by most vendors. Various standards and industry groups are looking further into ways to adopt and standardize the use of VHDL in the design process. This many faceted response is evidenced by the large coverage of VHDL by the vendor community and press. The formation of the VHDL Users' Group was promoted by the Computer Society of the IEEE's Design Automation Standards Subcommittee. The Users' Group exists to provide a broad, user based forum for collecting, discussing, and disseminating information and sharing experience on the use of VHDL. The Fall 1989 Users' Group Meeting is targeted at the use of VHDL in the electronic design process. As such, participation is encouraged from all electronic designers, managers, and tool developers. Hillel has revamped the format to include much more discussion oriented sessions with attendee participation encouraged. Tutorials on Sunday serve to introduce newcomers to VHDL and its current role. Interested parties are encouraged to attend the Design Automation Standards Subcommittee meetings immediately following the Users' Group meeting. See the inside of this agenda or contact Larry Saunders, (507) 253-2509, for additional information. Randolph E. Harr General Chair -------------------------------------------------------------------------- Fall 1989 VHDL Users' Group Meeting Committee Randolph E. Harr, C.A.D.onomist General Chair Hillel Ofek, Amdahl Corporation Program Chair Dr. Alec Stanculescu, Fintronic USA, Inc. Program Co-Chair Joe Youmans, Hughes Aircraft Company Demonstrations Chair Dr. H. Edward Tsou, TRW Tutorial Chair Richard Hall, Vantage Analysis Systems, Inc. Publications Chair David R. Coelho, Vantage Analysis Systems, Inc. Finance Chair Merry Bush, Conference Management Services Registration and Publicity Chair With additional assistance and support from Amdahl, Fintronic USA, Hughes Aircraft Company, TRW, Vantage Analysis Systems, the Computer Society of the IEEE's DATC and the Electronic Industries Association. Under management of Conference Management Services. VHDL Users' Group Steering Committee Victor Berman, Intermetrics Dr. Harold Carter, University of Cincinnatti David Coelho, Vantage Analysis Systems, Inc. Randolph E. Harr, C.A.D.onomist Fred Hinchliffe, II, CAD Language Systems, Inc. Dr. John Hines, USAF WRDC Paul Hunter, Naval Research Laboratory Susan Johnston, Boeing Aerospace Company Ghulam Nurie, Daisy / Cadnetix, Inc. Hillel Ofek, Amdahl Corporation Rachel Rusting, Intermetrics Dr. Moe Shahdad, CAD Language Systems, Inc. Dr. H. Edward Tsou, TRW Ronald Waxman, University of Virginia Joe Youmans, Hughes Aircraft Company -------------------------------------------------------------------------- FALL 1989 VHDL USERS' GROUP MEETING Advanced Registration Form Sheraton @ Redondo Beach, CA 22-25 October 1989 Name ____________________________________ Phone __________________________ Affiliation _____________________________ M/S ____________________________ Street Address ____________________________________________________________ City ________________________ State ________________ Zip ________________ Make check payable to VHDL USERS' GROUP and mail it with this form to the address below. All advance registrations must be postmarked by 2 October 1989. By 2 Oct At Meeting Students General Sessions $ 160 $ 180 $ 90 Tutorial A $ 120 $ 140 $ 70 Tutorial B $ 120 $ 140 $ 70 ---------- Mail To: Spring 1989 VHDL Users' Group Meeting C/O Conference Management Services 408 Waverly Street Menlo Park, CA 94025 -------------------------------------------------------------------------- FALL 1989 VHDL USERS' GROUP MEETING Hotel Reservation Form Sheraton @ Redondo Beach, 22-25 Oct 1989 Please Print or Type Name _______________________________________ Phone ________________________ Affiliation ________________________________ Mail Stop ____________________ Street Address ____________________________________________________________ City _______________________ State __________________ ZIP _________________ This is a reservation request and must be accompanied by a one night room deposit or credit card guarantee. All advance registrations must be postmarked by 2 Oct 1989. Arrival Date: __________________ Time: ___________ Departure Date: __________________________________ (circle one) Single @ $80/night Double @ $90/night Credit Card Type: AX DC CB VISA MC Expiration Date: _________________ Credit Card #: ___________________________________ Signature: _______________________________________ Mail to: Sheraton @ Redondo Beach 300 North Harbor Drive Redondo Beach,CA 90277 or Call: (213) 318-8888 and ask for "VHDL Users' Group" rate -------------------------------------------------------------------------- PROGRAM Tutorials: Sunday, 22 October 1989: 1:00pm to 5:00pm (a) "Modeling in VHDL" Dave Barton, Intermetrics, Inc. (b) "Design Synthesis from VHDL" Dr. Dan Gajski, University of California at Irvine All tutorials include a refreshment break Registration: Sunday, 22 October 1989: Noon to 5:00 pm Monday, 23 October 1989: 7:30 am to Noon Special Interest Group Meetings: Tuesday, 24 October 1989: 7:00pm to 10:00pm (Topics to be arranged on site) VHDL Design Exchange Group Meeting: Sunday, 22 October 1989: 8:00am to 5:00pm IEEE Design Automation Standards Subcommittee (DASS) Meetings: Thursday - Friday, 26 - 27 October 1989: 8:00am to 5:00pm (The IEEE charges an extra fee to attend this meeting) General Sessions: Monday, 23 October 1989 8:30 am Welcome and Orientation (1) Randolph E. Harr, General Chair Hillel Ofek, Program Chair Keynote Address "Trends in Design Automation" Mr. Sonny Maynard Vice President, Engineering and Operations McDonnell Douglas Electronics Systems Company 10:00 Coffee Break 10:30 "User Experience: Designing with VHDL" (round table) A. Stanculescu, Fintronic USA, Inc. (chair) A VHDL Design Methodology used within IBM Q. Schmierer, IBM IBM Chip Designs done with VHDL R.D. Hoover, IBM VHDL in Honeywell: Setting the Pace F. Rose, Honeywell, Inc. The Honeywell Simulator Independent VHDL Design Environment J. Winkler, Honeywell SSEC VHDL and Logic Synthesis in Raytheon S. Lau, Raytheon 12:30 Lunch (on your own) 2:00 "Advanced Concepts" R. Niederland, McDonnell Douglas (chair) Measuring the Complexity of VHDL Specifications G. Aharonian, Source Translation & Optimization The Modeler's Assistant: A Graphical Approach to the Development of VHDL Behavioral Models D. Burnette, et.al., Mentor Graphics Corp. Operational Specifications in VHDL using Statechart Concepts R. MacDonald, et.al., University of Virginia Virtual Systems Integration with VHDL C.W. Rose, Zycad Corporation 3:30 Refreshment Break 4:00 "VHDL Modeling in Design" D. Azaren, TRW (chair) Basic Structures for High-Level VHDL Modeling E. Cerny, et.al., Universite de Montreal VHDL Behavioral Models for Fault Simulation of Higher Level Packages T.M.Elliott, IBM Corporation Modeling of EPLD in VHDL C.H. Lee, Naval Postgraduate School A CPU Modeling Strategy; 80486 Implementation J. Jacobson, Intel Corporation 5:30 Reception to 7:00 Tuesday, 24 October 1989 7:30 Continental Breakfast 8:00 "VHDL Models for Simulation" (round table) Gabe Moretti, EIS Modeling, Inc. (chair) What is a VHDL Model? T. Johnson, et. al., Logic Automation Modeling Guidelines for Efficient Simulation K. Scott, Vantage Analysis Systems VHDL: Component Modeling D. Eggleston, Viewlogic Systems, Inc. A Detailed Look at Register-Transfer Level Modeling in VHDL for Accelerated Simulators B. La Porte, Zycad Corporation Hardware Modeling in the VHDL Environment H. Stump, Logic Modeling Systems, Inc. 10:00 Coffee Break 10:30 "User Experience: VHDL Applications" (round table) D. Perry, Vantage Analysis Systems (chair) Top down design in VHDL J. DeGroat, AFIT VHDL Model Generation B. Dixon, et.al., Rockwell International VHDL, Obsolescence and Technology Insertion F. Custode, et.al., Rockwell International VHDL Architecture Simulation of a Micro-Instruction Control Memory M.A. Tirabassi, TRW Electronic Systems Group VHSIC Bus Simulator Model Development - an Update S. Adamus, SAIC 12:30 Lunch (on your own) 2:00 "VHDL Simulation" (round table) K. Crossland, SAIC (chair) VHDL in DSP System Design and Synthesis L.G. Herlitz, et.al., Comdisco Systems, Inc. Simulation Performance Aspects of VHDL Constructs J. Sissler, HHB Systems, Inc. An Evolutionary Approach to Full VHDL A. Guyler, et.al., GenRad Ltd. Challenges to Creating a Concurrent Debugger for VHDL Simulations J. Kregel, Mentor Graphics 3:30 Refreshment Break 4:00 "Formalism in VHDL" D. Barton, Intermetrics, Inc. (chair) Problems in a Formal VHDL Semantics D. Barton, Intermetrics, Inc. An Introduction to VHDL Calculus A.N.D. Samfirescu, Vantage Analysis Systems, Inc. Towards a Formal Model of VHDL Data-Flow Descriptions L.M. Augustin, Stanford University A VHDL Synthesis Tool to Rapidly Prototype Neural Network Architectures G. Cubbage, Booz, Allen & Hamilton 5:30 Reception to 7:00 Wednesday, 25 October 1989 7:30 Continental Breakfast 8:00 "Towards Consistent VHDL Use" Myke Smith, Amdahl Corporation (chair) The VHDL Validation Suite: A Co-operative Industrial Effort J.R. Armstrong, et.al., Virginia Tech VHDL Validation Suite V. Berman, Intermetrics, Inc. The Finding and Training of VHDL Programmers and Designers J. Pick, Westinghouse Electric Corporation Proposal for a Working Group on Representing Electronic Data Book Information in VHDL / EDIF S. Kelam, Daisy / Cadnetix, Inc. VHDL Model Validation: A Plan for the Future J.S. Calhoun, Institute for Technology Development 10:00 Coffee Break 10:30 "VHDL Synthesis" (round table) D. Kliment, Rockwell International (chair) Synthesizing from VHDL Data Types S. Carlson, Synopsys, Inc. ASIC Design using VHDL Synthesis D. Gay, Viewlogic Systems, Inc. VHDL Design Styles for Synthesis and Silicon Compilation Z. Navabi, Northeastern University Structured Modeling for VHDL Synthesis J. Lis, et.al., University of California at Irvine Experiences Using VHDL in the Classroom S. Levitan, et.al., University of Pittsburgh 12:30 Lunch (on your own) 2:00 "VHDL Standards Update" L. Saunders, IBM (chair) IEEE CS DATC Design Automation Standards Subcommittee L. Saunders, IBM Corp. VHDL Analysis and Standardization Group Update S. Krolikoski, IBM Corp. The WAVES Standard Toolkit A. Gilman, et. al., Intermetrics, Inc. Interoperability of VHDL Models Using the VDEG Methodology G. Nurie, Daisy/Cadnetix Inc. EIA VHDL Model Standards and Development Update J. Willner, Hughes Aircraft Company 3:30 Refreshment Break 4:00 "Applying VHDL to Analog Design" S. Grout, MCC (chair) Analog Hardware Descriptive Language Requirements: IEEE Standards Coordinating Committee 30 Report J.M. Schoen, MITRE Corporation VHDL and Analog Modeling D.W. Smith, Analogy Inc. VHDL Modeling for Analog-Digital Hardware Designs M. Brown, IBM A VHDL Model for Pass Transistors used in the 6502 Microprocessor D.F. Hanson, University of Mississippi 5:30 Meeting Close -------------------------------------------------------------------------- Demonstrations: The Fall meeting will feature vendor, industry, and university demonstrations of VHDL systems and applications. These demonstrations will be open only to registered attendees during the meeting. The expected demonstrators are: CAD Language Systems, Inc. Mentor Graphics Corp. Comdisco Systems, Inc. Quadtree Software Daisy/Cadnetix Inc. Silicon Compiler Systems Corp. Gateway Design Automation Corp. Synopsys Inc. GenRad Inc. Vantage Analysis Systems, Inc. Harris Semiconductor Viewlogic Systems, Inc. Intermetrics, Inc. Vista Technologies, Inc. JRS Research Laboratories Inc. Zycad Corp. Demonstration Hours Monday, 23 October 1989, 12:30 pm to 8:00pm Tuesday, 24 October 1989, 12:30 pm to 8:00pm