----------------------------------------------------------------- -- CS61584A-IL (68-pin PLCC) BSDL File IEEE STD 1149.1 Sept 1990 -- -- Ver 1.0 November 1998 -- Tao Lang -- ----------------------------------------------------------------- entity CS61584A is generic (PHYSICAL_PIN_MAP : string := "PLCC_68"); -- Port Declarations -- Note that the "bidirectional" pins in the CS61584A -- are not all truly bidirectional and must be configured as -- either inputs or outputs - see datasheet -- PORT DESCRIPTION TERMS -- in = input only -- out = three-state output -- inout = bidirectional -- linkage = power, ground, analog) -- bit = single pin -- bit_vector = group of pins 0 to n port( ATTEN0, ATTEN1 : in bit; LLOOP, CLKE : inout bit; CON01, CON02 : inout bit; CON11. CON12 : inout bit; CON21 : inout bit; CON22 : in bit; CON31, CON32 : in bit; TAOS1, TAOS2 : inout bit; RLOOP1 : inout bit; RLOOP2 : in bit; TPOS1, TPOS2 : in bit; TNEG1, TNEG2 : inout bit; TCLK1, TCLK2 : in bit; RPOS1, RNEG1, RCLK1 : out bit; RPOS2, RNEG2, RCLK2 : out bit; PD1, PD2 : in bit; MODE, RESET : in bit; LOS1, LOS2 : inout bit; TMS, TDI, TCK : in bit; TDO : out bit; TV1, TV2, RV1, RV2 : linkage bit; AV, DV, AGND, BGREF, REFCLK, XTALOUT, CLKx1 : linkage bit; DGND1, DGND2, DGND3 : linkage bit; TGND1, TGND2, RGND1, RGND2 : linkage bit; TTIP1, TRING1, RTIP1, RRING1 : linkage bit; TTIP2, TRING2, RTIP2, RRING2 : linkage bit; Not_Used : linkage bit_vector(1 to 4)); use STD_1149_1_1990.all; attribute PIN_MAP of CS61584A : entity is PHYSICAL_PIN_MAP; -- Physical Pin Mapping constant PLCC_68 : PIN_MAP_STRING := "ATTEN0:25, ATTEN1:8," & "LLOOP:5, CLKE:44, CON01:2, CON02:66, CON11:65," & "CON12:64, CON21:63, CON22:62, CON31:61, CON32:52," & "TAOS1:4, TAOS2:3, RLOOP1:7, RLOOP2:6, TPOS1:14," & "TPOS2:55, TNEG1:15, TNEG2:54, TCLK1:13, TCLK2:56," & "RPOS1:11, RNEG1:12, RCLK1:10, RPOS2:58, RNEG2:57," & "RCLK2:59, PD1:24, PD2:45, MODE:31, RESET:35," & "LOS1:16, LOS2:53, TMS:50, TDI:19, TCK:51, TDO:17," & "TV1:21, TV2:48, RV1:29, RV2:40, AV:34, DV:68," & "AGND:33, BGREF:32, REFCLK:36, XTALOUT:37, CLKx1:38," & "DGND1:1, DGND2:18, DGND3:67, TGND1:22, TGND2:47," & "RGND1:30, RGND2:39, TTIP1:20, TRING1:23, RTIP1:27," & "RRING1:28, TTIP2:49, TRING2:46, RTIP2:42, RRING2:41," & "Not_Used : (9, 26, 43, 60)"; -- Compulsory signal Attribute Declarations attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (4.0e6,LOW); attribute INSTRUCTION_LENGTH of CS61584A: entity is 2; attribute INSTRUCTION_OPCODE of CS61584A: entity is "BYPASS (11)," & "EXTEST (00)," & "SAMPLE (01)," & "IDCODE (10)"; attribute INSTRUCTION_CAPTURE of CS61584A: entity is "01"; attribute IDCODE_REGISTER of CS61584A: entity is "0000" & "0000000000000011" & "00001100100" & "1"; attribute REGISTER_ACCESS of CS61584A: entity is "BOUNDARY (SAMPLE, EXTEST), " & "BYPASS (BYPASS)," & "IDCODE (IDCODE) "; attribute BOUNDARY_CELLS of CS61584A: entity is "BC_1"; attribute BOUNDARY_LENGTH of CS61584A: entity is 62; attribute BOUNDARY_REGISTER of CS61584A: entity is -- PORT DESCRIPTION TERMS -- cell type: BC_1 -- port: port name -- input = input only -- bidir = bidirectional -- control = control cell -- output3 = three state output -- safe = value in control cell to make input = 0 for bidir and control -- ccell = controlling cell number for I/O direction -- dsval = disabling (input) value -- rslt = result if disabled (input = Z) --num cell port function safe ccell dsval rslt " 0 ( BC_1, *, control, 0), "& " 1 ( BC_1, LOS1, output3, 0, 0, 0, Z), "& " 2 ( BC_1, LOS1, input, X), "& " 3 ( BC_1, *, control, 0), "& " 4 ( BC_1, TNEG1, output3, 0, 3, 0, Z), "& " 5 ( BC_1, TNEG1, input, X), "& " 6 ( BC_1, TPOS1, input, X), "& " 7 ( BC_1, TCLK1, input, X), "& " 8 ( BC_1, *, control, 0), "& " 9 ( BC_1, RNEG1, output3, 0, 8, 0, Z), "& " 10 ( BC_1, *, control, 0), "& " 11 ( BC_1, RPOS1, output3, 0, 10, 0, Z), "& " 12 ( BC_1, *, control, 0), "& " 13 ( BC_1, RCLK1, output3, 0, 12, 0, Z), "& " 14 ( BC_1, ATTEN1, input, X), "& " 15 ( BC_1, *, control, 0), "& " 16 ( BC_1, RLOOP1, output3, 0, 15, 0, Z), "& " 17 ( BC_1, RLOOP1, input, X), "& " 18 ( BC_1, RLOOP2, input, X), "& " 19 ( BC_1, *, control, 0), "& " 20 ( BC_1, LLOOP, output3, 0, 19, 0, Z), "& " 21 ( BC_1, LLOOP, input, X), "& " 22 ( BC_1, *, control, 0), "& " 23 ( BC_1, TAOS1, output3, 0, 22, 0, Z), "& " 24 ( BC_1, TAOS1, input, X), "& " 25 ( BC_1, *, control, 0), "& " 26 ( BC_1, TAOS2, output3, 0, 25, 0, Z), "& " 27 ( BC_1, TAOS2, input, X), "& " 28 ( BC_1, *, control, 0), "& " 29 ( BC_1, CON01, output3, 0, 28, 0, Z), "& " 30 ( BC_1, CON01, input, X), "& " 31 ( BC_1, *, control, 0), "& " 32 ( BC_1, CON02, output3, 0, 31, 0, Z), "& " 33 ( BC_1, CON02, input, X), "& " 34 ( BC_1, *, control, 0), "& " 35 ( BC_1, CON11, output3, 0, 34, 0, Z), "& " 36 ( BC_1, CON11, input, X), "& " 37 ( BC_1, *, control, 0), "& " 38 ( BC_1, CON12, output3, 0, 37, 0, Z), "& " 39 ( BC_1, CON12, input, X), "& " 40 ( BC_1, *, control, 0), "& " 41 ( BC_1, CON21, output3, 0, 40, 0, Z), "& " 42 ( BC_1, CON21, input, X), "& " 43 ( BC_1, CON22, input, X), "& " 44 ( BC_1, CON31, input, X), "& " 45 ( BC_1, *, control, 0), "& " 46 ( BC_1, RCLK2, output3, 0, 45, 0, Z), "& " 47 ( BC_1, *, control, 0), "& " 48 ( BC_1, RPOS2, output3, 0, 47, 0, Z), "& " 49 ( BC_1, *, control, 0), "& " 50 ( BC_1, RNEG2, output3, 0, 49, 0, Z), "& " 51 ( BC_1, TCLK2, input, X), "& " 52 ( BC_1, TPOS2, input, X), "& " 53 ( BC_1, *, control, 0), "& " 54 ( BC_1, TNEG2, output3, 0, 53, 0, Z), "& " 55 ( BC_1, TNEG2, input, X), "& " 56 ( BC_1, *, control, 0), "& " 57 ( BC_1, LOS2, output3, 0, 56, 0, Z), "& " 58 ( BC_1, LOS2, input, X), "& " 59 ( BC_1, CON32, input, X), "& " 60 ( BC_1, PD2, input, X), "& " 61 ( BC_1, PD1, input, X), "& end CS61584A; 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