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Zilog 85230 White Paper
The PC industry has seen tremendous improvements in processing power and CPU speed. As CPU speed and overall system performance increases, PC chip sets also have become faster. Newer Pentium machines operate much faster than older ‘486 and ‘386 machines. The newer speed combined with the fact that no real PC/AT bus timing spec exists may cause problems with older ISA cards that perform Direct Memory Access (DMA). This White Paper is dedicated to the discussion of the Zilog 8530, 85C30 and 85230 Serial Communications Controller (SCC) and particularly the Recovery Time Requirements (the minimum time between accesses) of the chip. If the SCC is to be integrated with a Pentium class or higher machine, this paper is very relevant.
Per the Zilog SCC Data Book, the length of the SCC recovery time is 4 PCLKS. The PLCK on a standard ACB is 4.9152 MHz. This relates to a recovery time of 4 / 4.9152E6 or 813.8 nano seconds (ns). The recovery time will shorten if the oscillator on an ACB is changed to a higher value (i.e. 20MHz recovery time = 200ns). Through evaluation and testing, Sealevel has determined that the optimal recovery time should be less than 660ns. To accomplish this we are replacing the 4.9152 MHz oscillator with a 7.3728 MHz oscillator. This oscillator will support the same baud rates currently available with the 4.9152 MHz oscillator and provide a recovery time of 542ns (which is less than the required 660ns).
If the adapter in question is to be used in a synchronous mode, where the transmit and receive clock is provided by the DCE device, this oscillator change is not an issue, as the clocking for the SCC is provided by the external device. There is no particular clock spec for the external clock, other than that it be within the operating range of the SCC. If the requirement is for asynchronous data communications, or for the ACB adapter to provide clocks, a change must be made to the SCC programmable baud rate registers (Write Registers 12 and 13). These registers contain the time constant used to set the required baud rates. As the baud rate is a function of the PCLK, changing the PCLK will affect the baud rate calculation. Please refer to the Zilog SCC Handbook, the Advanced Communications Board Developer’s Toolkit Disk, or your SeaMAC help file for information on calculating these time constants/divisors.
The table below will display some traditional baud rates and divisors for both the 4.9152 MHz oscillator and the 7.3728 MHz oscillator. (Since asynchronous data rates are the most effected, all rates will be using the 16x clock.). We apologize for any inconvenience and offer, as always, our excellent technical support staff to assist with any questions or concerns that this issue may cause.
4.9152 MHz Oscillator
(values in Hex) |
Data Rate
(bits/sec) |
7.3728MHz Oscillator
(values in Hex) |
| WR12 |
WR13 |
|
WR12 |
WR13 |
| 7E |
00 |
1200 |
BE |
00 |
| 1E |
00 |
4800 |
2E |
00 |
| E |
00 |
9600 |
16 |
00 |
| 6 |
00 |
19.2 |
0A |
00 |
| 2 |
00 |
38.4 |
4 |
00 |
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