Answers Database

A1.4/F1.4 Bitgen - Bad 5200 bitstream is created for IOB routethrus and CLB latches


Record #3438

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
A1.4/F1.4 Bitgen - Bad 5200 bitstream is created for IOB routethrus and
CLB latches



Problem Description:
The following two problems exist in both Alliance (A1.4) and Foundation (F1.4)
for 5200 bitgen.


1. If an IOB routethru is used, the IOB will not be configured
   properly.

2. If a CLB latch is used, the clock polarity will not be properly
   set for LC1, LC2 and LC3.



Solution 1:

A patch is available on the Xilinx Download area:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/bit_5200.zip
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/bit_5200.tar.Z

This patch should be applied to both A1.4 and F1.4 products.

This fix is also  included in the Core Tools #5 patch,
which also contains some other 5200 related fixes for PAR:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z



End of Record #3438