New -08 Speed Grade Available
Now for Select Devices
The
3.3V XC4000XL family takes the XC4000 Series to new heights in density
and performance. The XC4000XL delivers industry-leading system performance
of up to 80MHz while minimizing power consumption. It features 11 family
members with Select-RAM™, ranging in density from 466 to 7,448 logic cells
(up to 180K system gates). The fully 5-volt tolerant I/Os solve interface
problems in mixed 5V-3V systems. For high-volume applications, mask programmed
HardWire™ versions are available.
Family Highlights
Features
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-08 speed grade available for XC4013XL, XC4036XL,
XC4062XL
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3.3 volt operation / 5.0 volt compatibility
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11 family members
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2K to 180K system gates
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Select-RAM memory, fully synchronous timing, true
dual-port capability IEEE 1149.1-compatible boundary scan logic
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Internal 3-state bus capability
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12mA sink current per output
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Wide edge decoders
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Highest Density
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466 to 7,448 logic cells (4-input look-up-table and
flip-flop)
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Up to 180K system-level gates
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Up to 448 user I/O pins
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Advanced CMOS Process Technology
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0.35µ CMOS process, 3.3V power supply
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Fully 5V-tolerant I/Os
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Unlimited reprogrammability
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Immune to latch-up (no power supply sequencing constraints)
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Highest Performance
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90+ MHz real system performance
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Up to 102MHz chip-to-chip I/O speed
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135MHz dual-port RAM
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100MHz 12x12 multiplier accumulator
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100MHz 24-bit loadable accumulator
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Ultra-high performance DSP functions
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3.0 billion MACs/s for 8x8 full precision in XC4062XL
(1.0 billion @ 12x12)
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Performance Predictability*
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Advanced Low-power Routing Architecture
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High-speed, buffered, segmented interconnect
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Eight high-speed, low-skew global clocks
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Abundant routing resources for up to 100% device
utilization
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VersaRing™ I/O interface for the best pin-locking
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Complete Alliance™ and Foundation Series™ Software Support
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Windows 95, Chinese, Korean, Japanese, Windows NT,
NEC98
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Solaris, HP-UX, AIX
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Standard-based (VHDL, Verilog, EDIF, SDF)
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Complete design solution with Foundation Series
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Powerful tools integrated into your EDA Environment
with Alliance Series
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Generates and delivers parameterizable cores optimized
for Xilinx FPGAs with CORE Generator
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Distributed
High-performance Select-RAM
Select-RAM Flexibility
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Build as many high-performance RAM blocks as needed
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Each block cascadable to any width and depth
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Placed at any desired location within the FPGA
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Ideal for functions such as FIFOs, DSP filters, accumulators,
and scratch-pad memories
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Power Roadmap (for constant number of gates and same
frequency)
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PDF files below.
