Answers Database
XC3100:Timing of Direct Connects
Record #106
Problem Title:
XC3100:Timing of Direct Connects
Problem Description:
XC3100: Direct Connect Timing
Solution 1:
Although the direct connects on the faster XC3000 speed grades (-100
and above) are assigned a delay of zero, the direct connect delay on
XC3100 devices is not zero. The timing models differ between the XC3000
and XC3100 families. The non-zero delay in the XC3100 prevents the double
counting of delays elsewhere in the model.
End of Record #106
For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals! |