Answers Database

XC4000: Table of Connections To and From BUFGP and BUFGS


Record #107

Product Family:  Hardware

Product Line:  4000

Problem Title:
XC4000: Table of Connections To and From BUFGP and BUFGS


Problem Description:
XC4000: Table Describing Direct Sources and Loads of BUFGP and BUFGS


Solution 1:

XC4000: Connections To and From BUFGP and BUFGS


For primary global buffers:

BUFGP in Corner 		  Sourced by IOB	       Drives CLB Pins
--------------- 	 -------------- 	  ---------------
TL (top left)				    PGCK1			    K an
d F3

BL (bottom left)			 PGCK2				 K and G
1

BR (bottom right)		       PGCK3			       K and C3

TR (top right)				  PGCK4 			  K and
C1

For secondary global buffers:

BUFGS in Corner 		  Sourced by IOB	       Drives CLB Pins
--------------- 	 -------------- 	  ---------------
TL (top left)				    SGCK1		     K, F3, G1,
C3 and C1

BL (bottom left)			 SGCK2			  K, F3, G1, C3
and C1

BR (bottom right)		       SGCK3			K, F3, G1, C3 an
d C1

TR (top right)				  SGCK4 		   K, F3, G1, C3
 and C1




Solution 2:

XC4000/E
========

All IOB inputs can be driven by BUFGP and BUFGS; however,
only T, OK (output clock), and IK (input clock) can be
directly driven by the global buffers (Refer to page 4-39 of
the 1996 data book).

To get to CE(4000E Only) and O in the IOB, the global clock
signal must first go through a CLB.  Through one of the C(1-4)
inputs, though the bypass mux, and out of YQ or XQ (Refer to
page 4-12 of the 1996 data book).

After leaving the CLB, the signal can go out to a single
length line which has access to the CE(4000E) or O pin of the
IOB.



Solution 3:

For more information about theses connections including
diagrams of the BUFGP and BUFGS of the XC4000 family,
please consult pages 3-2 ans 3-3 of the HDL Synthesis
for FPGAs Design Guide.



End of Record #107