Answers Database

XC3000/XC4000/XC4000: Clock Buffers- (ACLK GCLK BUFGP BUFGS): When to use them


Record #126

Problem Title:
XC3000/XC4000/XC4000: Clock Buffers- (ACLK GCLK BUFGP BUFGS): When to
use them



Problem Description:



Solution 1:




3000 family global buffers:

	The GCLK and ACLK buffers are normally only useful
for routing clock nets (those nets that only go to CLB and
IOB 'K' pins.  If one must be used as a source for other
types of loads, the ACLK buffer is the only choice, as
it is the only one of the two which can access non-clock
pins.


4000 family global buffers:

	There are two global buffers located in each corner
of a 4000 die, one a primary buffer and one a secondary
buffer.  Although this technically gives a total of eight
available buffers, one must be careful when using more
than four or when using the buffers for sourcing non-clock
loads.	The  buffers have the ability to make direct
(non-feedthrough) connections to the  following pins:

BUFGS LOCATION			DIRECT-CONNECT TO CLB PINS
--------------			--------------------------

TL				K,F3,G1,C3, and C1
BL				K,F3,G1,C3, and C1
BR				K,F3,G1,C3, and C1
TR				K,F3,G1,C3, and C1

BUFGP LOCATION			DIRECT-CONNECT TO CLB PINS
--------------			--------------------------

TL				K and F3
BL				K and G1
BR				K and C3
TR				K and C1


There are four vertical global lines in each column of a 4000
die that are reserved for use by global buffers.  A specific
BUFGP can access only one specific global line.  A BUFGS,
however, may use any of the four global lines. This accounts
for the difference in the above two tables.  It is important
to note that PPR versions 1.31 and earlier did not
intelligently select which buffer to use for a given net.
For example, PPR may arbitrarily choose to  use the TL BUFGP
for a clock enable net.  Clock enable nets require access to
the C pins of the CLBs.  Since the TL BUFGP may only access
the global line that directly connects to the K and F3 pins
of CLBs, the net will then have to be routed using
feedthroughs.  A simple placement constraint on the BUFGP
would resolve this.

Since there are only four vertical global lines in each
column, placement and routing may be somewhat complicated by
the use of more than four global buffers
of any kind. For example, if four BUFGS buffers and one BUFGP
buffer were all used for clock nets (the least complicated
case), PPR may place five CLBs in a column which all contain
flip-flops with unique clocks.	Thus, the router is left with
the task of routing five global clock nets using four
vertical global lines, again requiring the use of
feedthroughs.  The problem becomes even more complicated if
some of the nets are non-clock nets!  These situations
normally require the use of placement constraints on CLB
locations to assure that not more than four global loads are
placed within the same column.	It is certainly far from
impossible to use more than four global buffers, but use of
more must be done intelligently.





End of Record #126