Answers Database

XBLOX gives error "Cannot create XIF" on Concept design


Record #216

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
XBLOX gives error "Cannot create XIF" on Concept design


Problem Description:
XBLOX returns "Cannot create XIF" on a Cadence Concept design containing
ELEMENT, SLICE or BIDIR_IO symbols.  The problem is specific to Concept
releases 9302 through 9304.

There were a number of errors in the Xilinx XBLOX Concept libraries in
these releases.  Specifically, the pin directions are wrong for these XBLOX
symbols:

1. The BIDIR_IO symbol's `INPUTS' should be an output, not an input.

2. The ELEM on the ELEMENT symbol should be an input, not an output.

3. The SUB on the SLICE symbol should be an input, not an output.


Solution 1:

Edit the XNF file to correct these pin directions.  For example:

ELEMENT:

   SYM, LCA2_ADEC1P_LMN19P, ELEMENT, DEF=BLOX, =ELEM=9
   PIN, XBLOX_BUS, I, LCA2_ADEC1P_X2
   PIN,  ELEM,	O,  <signal_name>
   END

The third line should read:  PIN, ELEM, I, <signal_name>

SLICE:

   SYM, LCA2_ADEC1P_SLC21P, SLICE, DEF=BLOX, =SLICE=12:9, =SUB=,
      =SUB_STARTS_AT=
   PIN, SUB, O, LCA2_ADEC1P_X1
   PIN, MAIN, I, CPU68_ADR
   END

The second line should read:  PIN, SUB, I, LCA2_ADEC1P_X1

BIDIR_IO:

   SYM, LCA2_BDR36P, BIDIR_IO, DEF=BLOX, =ENCODING=UBIN, =BOUNDS=7:0
   PIN, OUTPUTS, I, CPU68_DATA_READ
   PIN, OE, I, N_68CPU_DATA_OE
   PIN, INPUTS, I, CPU68_DATA_WRITE
   END

The fourth line should read:  PIN, INPUTS, O, CPU68_DATA_WRITE



End of Record #216