Answers Database

VIEWsynthesis: Infering an xc4000 `set' flip-flop or an inverted xc3000`reset' flip-flop


Record #246

Product Family:  Software

Product Line:  ViewLogic

Problem Title:
VIEWsynthesis:  Infering an xc4000 `set' flip-flop or an inverted
xc3000`reset' flip-flop



Problem Description:



Solution 1:

XC4000 designs:

  By default, the Viewlogic synthesis tools infer a reset flip-flop (FDCE).

  For XC4000 designs, you can infer a set flip-flop (FDPE) using the
  following code example:

--  Infering an xc4000 FDPE with its CE pin tied to VDD

entity try is
  port (
    din  : in  bit;
    clk  : in  bit;
    qout : out bit;
    set  : in  bit
  );
end try;

architecture one of try is
begin
  process
  begin
    wait until prising(clk) or set = '1';
    if (set='1') then
      qout <= '1';
    else
      qout <= din;
    end if;
  end process;
end one;

-- end of xc4000 FDPE example

XC3000 designs:

  Because the xc3000 family of devices do not have set type flip-flops
  only reset type flip-flops can be infered.

  To invert the polarity of an xc3000 flip-flop, use the following code
  example:

-- Inverting the polarity of an xc3000 reset flip-flop (FDCE) with its
-- CE pin tied to VDD

entity try is
  port (
    din  : in  bit;
    clk  : in  bit;
    qout : out bit;
    set  : in  bit
  );
end try;

architecture one of try is
  signal qouttemp : bit;
  signal dintemp  : bit;
begin
  process
  begin
    wait until prising(clk) or set = '1';
    if (set='1') then
      qouttemp <= '0';
    else
      qouttemp <= dintemp;
    end if;
  end process;

  dintemp <= not din;
  qout <= not qouttemp;

end one;

-- end of xc3000 FDCE example




End of Record #246