Answers Database

XBLOX 5.x: Implementing DATA_REG in IOB resources


Record #260

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
XBLOX 5.x: Implementing DATA_REG in IOB resources


Problem Description:
How do I force DATA_REG to be implemented in an I/O block?


Solution 1:

The following STYLE attributes, new in XACT 5.0, are available on the
DATA_REG module to control where the DATA_REG flip-flops are placed.

   * STYLE=IOB: Implement as either IFDs or OFDs (input FF or output FF)
   * STYLE=IFD: Implement as IFDs (input FFs)
   * STYLE=OFD: Implement as OFDs (output FFs).
   * STYLE=ILD: Implement as ILDs (level-sensive input latches)
   * STYLE=CLB: Implement in CLB FFs

If you do not specify a style, XBLOX will select the appropriate style
based on how the DATA_REG is connected.  For example, in an XC4000, if the
DATA_REG is connected to an INPUTS symbol and does not use a clock enable,
the DATA_REG will be merged into the input flip-flops.	Otherwise, the
DATA_REG will use CLB flip-flops.



End of Record #260