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Minimum delay specifications for Xilinx devices.


Record #271

Problem Title:
Minimum delay specifications for Xilinx devices.


Problem Description:
keywords: timing, minimum, delay

Urgency: Standard

General Description:  Xilinx currently only provides specifications for maximum
delay values. When doing asynchronous designs ( not recommended in FPGAs ) or in
terfacing to external logic, minimum delays may become important. Mimimum delays
 can be calculated by taking 25% of the specified maximum delay values in the da
ta book for the fastest speed grade of a given part.


Solution 1:

The problem with mininimum specifications:

In CMOS technology, all delays decrease when the temperature
is lowered and when the supply voltage is increased.
Therefore, Xilinx test devices at a high temperature (85 C
junction temperature) and a low supply voltage (4.75V for
5V commercial parts).

If we call this specified and guaranteed delay 100%, how
short can it be "best case"?

o  Subtract 10% for tester guardband (Xilinx always test
tighter than promise, in order to avoid disagreements over
tester calibration. 10% may be ultra-conservative, but 5%
would be aggressive)

o  Subtract 10% for the difference between 4.75V test and
5.25V best case supply voltage.

o  Subtract 25% to 30% for the difference between 85 C test
and 0 C best case junction temperature.

o  Subtract 40% for the difference between our slowest
processing and fastest processing. Xilinx can catch some of
that by speed-binning, but (as mentioned before) all
manufacturers takes the liberty of "down-binning",
i.e. shipping a faster device into a slow order.

o  Multiply 0.9 x 0.9 x 0.7 x 0.6 and you get 0.34
That means, you can expect to get a best-case delay of about
a third of the specified value. And the difference is even
larger for industrial and military parts, and also larger
when we consider processing improvements from year to year.

For any given parameter, Xilinx suggest that you assume a
best-case value of 25% of the number that we specify for the
same parameter at the fastest available speed grade. Thus,
for the top-of-the-line fastest part, the ratio between
worst and best case delay is 4:1, for slower parts it is a
larger ratio. Internal to the chip, Xilinx guarantees that
min delays will never cause hold-time problems.

The customer may question that min delays are necessary for
if there is clock skew or positive hold times.	However, Xilinx
inputs have an added delay (optional in XC4000) that guarantees
that there is no data hold time even on the chip input.
For the XC4000 families, Xilinx also specifies guaranteed
pin-to-pin parameters, including set-up and hold times between
data and clock inputs.

Keeping clock skew between chips close to zero is the
obligation  of the systems designer. (Note:  that clock skew in
a direction opposite to the data flow is safe, only sacrifices
performance.)

Note: Design synchronously, whenever possible. A synchronous
design is inherently insensitive to min delays.



Solution 2:

Some specifics about guardbanding:

Xilinx actually test all commercial devices at 4.75 V and 85 degree
temperature. The tests take only a few seconds and create very little
power dissipation, so we preheat the devices to slightly more than 85
degrees C and then perform the test. Junction temperature is then only
very little above case temperature, which is 85 degrees centrigrade.

A device that fails any ( even a single ) test limit under these
conditions is rejected for this speed grade and is then tested for a
slower speed grade.

We have measured the temperature coefficient of delay parameters, and
we assume it to be between 0.25 and 0.35% per degree C.  The voltage
dependence of the delay parameters is roughly inversely proportional.
( Not all parameters behave the same way, because there are several
different physical phenomena involved here. That's why we cannot test at
room temperature and just calculate the worst-case values. We actually
test under the guaranteed worst-case operating conditions )

You can expect a 5% improvement in performance when you run at 5.00 V,
and a 15 to 20% improvement when you run at room temperature and low
power consumption, i.e. a junction temperature close to 25 degrees.
When you multiply 0.95 times 0.80 you get 0.76 for the delay, or 1.316
for the clock rate.

By the way, all semiconductor manufacturers also reserve the right to
"downbin", i.e. to mark a fast part with a slower speed grade than it
really is, when the market demand is higher for slower parts.

Designers should assume that a device can be up to four times faster
than the worst-case spec ( that also covers ambient conditions ), but
never slower than the worst-case spec.



End of Record #271