Answers Database

XBLOX 5.x: I/O signals disappear in simulation


Record #315

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
XBLOX 5.x: I/O signals disappear in simulation


Problem Description:
I/O signal names (underneath INPUTS, OUTPUTS, and BIDIR_IO) disappear in
simulation.


Solution 1:

The naming of I/O pads has changed in this release.  For example, consider
an INPUTS module with an instance name of SYM_LABEL, connected to a bus
called BUS_LABEL.  In releases prior to XBLOX 5.0, the names placed on the
pads were called:

   SYM_LABEL/BUS_LABEL<0>, SYM_LABEL/BUS_LABEL<1>, ...

In XBLOX 5.x, the default names are now:

   SYM_LABEL/PAD<0>, SYM_LABEL/PAD<1>, ...

(In both cases, the brackets do not appear in Viewlogic net names, e.g.,
SYM_LABEL/PAD0.)

You can control the pad name used by XBLOX with the PADNAME=new_label
attribute.  Attaching this attribute on the INPUTS, OUTPUTS, or BIDIR_IO
results in the following signal names:

   SYM_LABEL/new_name<0>, SYM_LABEL/new_name<1>, ...

To make your simulation run as with the pre-5.0 releases, you can either
change your simulation command files, or place the attribute PADNAME=PAD on
each XBLOX I/O block in the schematic.



End of Record #315