Answers Database

XBLOX 5.x models DATA_REG of STYLE=ILD as flip-flops in functional simulation


Record #317

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
XBLOX 5.x models DATA_REG of STYLE=ILD as flip-flops in functional
simulation



Problem Description:
If the XBLOX component DATA_REG is used with STYLE=ILD and XSimmake is run
to generate a functional simulation for the design, it is modeled as a set
of edge-triggered flip-flops, even though during actual implementation and
timing simulation, the correct level-sensitive latches are synthesized.
This is because XBLOX is run in its "simulation-only" mode that merely
creates simulation models for design components.  No architectural
optimizations are performed, including the placement of DATA_REG elements
into their user-defined places.  This causes the DATA_REG elements to be
treated as regular edge-triggered flip-flops and not the desired input
latches.


Solution 1:

The only workaround is to actually remove the DATA_REG with the STYLE=ILD
and replace it with the equivalent soft macros.



End of Record #317