Answers Database

XBLOX 5.x: XC3000A data registers not mapped with combinational logic


Record #320

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
XBLOX 5.x: XC3000A data registers not mapped with combinational logic


Problem Description:
When targeting an XBLOX design to an XC3000A device, XBLOX 5.x does some
mapping that may adversely affect design performance and CLB utilization.
There are many cases where an XBLOX symbol such as an ADD_SUB or PROM is
followed by a data register, but XBLOX maps the combinational logic so that
the data register is implemented in a separate CLB, even though both could
fit into the same CLB.	This results in extra net delays and wastes the
equivalent of an entire CLB per bit.

There are three workarounds for this problem.


Solution 1:

In the case of ADD_SUBs, use STYLE=RIPPLE.  This should cause XBLOX not to
generate mapping information for the adder, although it generally gives
worse performance than STYLE=FAST3KA (the default).



Solution 2:

Manually remove the CLBMAP symbol records associated with the symbol from
the XNF file.



Solution 3:

Use the -m option to XNFMap.  This forces XNFMap to ignore ALL mapping
information, which may be undesirable if you wish to retain other mapping
information.



End of Record #320