Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


PPR 5.0: Possible cause of Segmentation or Memory Protection faults (TNMs)


Record #360

Problem Title:
PPR 5.0: Possible cause of Segmentation or Memory Protection faults
(TNMs)



Problem Description:



Solution 1:




If using several TNMs on related logic paths, PPR may run into trouble
while mapping the associated logic to function generators.  If there
is more than one TNM in a logic path being mapped to a function
generator, PPR handles this by concatenating all of them into one
large TNM for the function generator.  However, if many TNMs are used
or they have large names then this may exceed the size PPR can handle
and it will crash without explanation.

One simple fix is to use TNMs with shorter names. However, it is
better to take the TNMs out of the logic path and place them on
endpoints, such as flip-flops, instead.




End of Record #360

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents