Return to Support Page
 homesearchagentssupportask xilinxmap

Answers Database


What is the fastest pin to pin delay?


Record #362

Product Family:  Hardware

Product Line:  7300

Problem Title:
What is the fastest pin to pin delay?


Problem Description:
What is the shortest pin-to-pin path through an XC7300 device, and
how can this delay be achieved?


Solution 1:

The fastest asynchronous path through an XC7300 device is tPDFO.  This is
the parameter being referenced when an XC7300 speed grade is specified.

tPDFO is the path from a fast input pin through one level of Fast Function Block

logic to an output pin.

This path can be specified by flagging inputs as fast inputs (using the (FI) or

.FI syntax in PLUSASM designs, or the F net attribute in schematic designs).
The associated output pin should be assigned to a Fast Function Block if necessa
ry,
and cannot use more than 4 product terms when implemented as an active
low equation.



End of Record #362

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals!

© 1998 Xilinx, Inc. All rights reserved
Trademarks and Patents