Answers Database

XC4000 Readback: How to work around rdclk max high and low time specs


Record #457

Problem Title:
XC4000 Readback: How to work around rdclk max high and low time specs


Problem Description:



Solution 1:




DEVICE FAMILY: 4000

DEVICE TYPE: All

CONFIGURATION MODE: n/a

SHORT DESCRIPTION:

The rdclk max high and low time can be ignored if certain rules are followed.

LONG DESCRIPTION:

PROBLEM:

The readback clock (rdclk) max high and low time is 50 uS according to P. 8-44
in the 94 databook.  In some cases, this spec can not always be met. For
example, if a processor is controlling readback, an interrupt may force it to
stop in the middle of a readback, which necessitates stopping the clock, and
thus violating the specification.

CAUSE:

The spec is mandatory only on clocking data at the end of a frame prior to the
next start bit.  The transfer mechanism will load the data to a shift register
somewhere, beginning 6 clock cycles before the start bit.  This loading process
is dynamic, and is the source of the max high and low time requirements.

Therefore, the spec applies to the 6 clock cycles prior to and including
any start bit (including the clocks before the first start bit in the readback
stream).

SOLUTION:

The spec does not apply when clocking out data from the middle of a data
frame.	At this time, the frame data is already in the register and the
register is not dynamic.  Thus, it can be shifted out just like a regular
shift register.  If the user can precisely calculate the location of the
readback data relative to the frame, he or she can park the clock either high
or low as long as they want in the readback process provided that it is not
during the times specified above.

NOTE: This is a non-trivial exercise, and should only be attempted by
      experienced users.




End of Record #457