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SYNOPSYS/BSCAN: How to instantiate BSCAN in the 4k/5k in Verilog/VHDL inSynopsys(FPGA Compiler,Design Compiler,FPGA Express)


Record #488

Product Family:  Software

Product Line:  Synopsys

Problem Title:
SYNOPSYS/BSCAN: How to instantiate BSCAN in the 4k/5k in Verilog/VHDL
inSynopsys(FPGA Compiler,Design Compiler,FPGA Express)



Problem Description:
To use boundary Scan in Xilinx devices, you must instantiate the boundary scan
symbol (BSCAN) and the associated dedicated I/O, and use the "dont_touch"
attribute; otherwise it is possible that BSCAN will be deleted by Synopsys.

Note, the code examples for instantiaing BSCAN will work with
FPGA Express v1.2 and FPGA Compiler/Design Compiler.  Note FPGA Express
is not a script driven tool.  The compile scripts only apply to
the FPGA Compiler/Design Compiler flow.





Solution 1:

I. VHDL Code for Instantiating BSCAN in the XC5200:

-- XC5200 example of instantiating the BSCAN symbol

entity example is
	port (a, b: in bit; c: out bit);
end example;


architecture xilinx of example is

component BSCAN
  port(tdi, tms, tck: in bit; tdo: out bit);
end component;

component TCK
  port ( I : out bit );
end component;

component TDI
  port ( I : out bit );
end component;

component TMS
  port ( I : out bit );
end component;

component TDO
  port ( O : in  bit );
end component;

component ibuf
	port (i: in bit; o: out bit);
end component;

component obuf
	port(i: in bit; o: out bit);
end component;

signal tck_net, tck_net_in  : bit;
signal tdi_net, tdi_net_in  : bit;
signal tms_net, tms_net_in  : bit;
signal tdo_net, tdo_net_out  : bit;

begin


u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net, tdo=>tdo_net_out);


u2: ibuf port map(i=>tck_net_in, o=>tck_net);
u3: ibuf port map(i=>tdi_net_in, o=>tdi_net);
u4: ibuf port map(i=>tms_net_in, o=>tms_net);

u5: obuf port map(i=>tdo_net_out, o=>tdo_net);

u6: TCK port map (I=>tck_net_in);
u7: TDI port map (I=>tdi_net_in);
u8: TMS port map (I=>tms_net_in);

u9: TDO port map (O=>tdo_net);

process(b)
begin
if(b'event and b='1') then
 c <= a;
end if;
end process;


end xilinx;







Solution 2:

II. Verilog Code for Instantiating BSCAN in the XC4000
NOTE: VERILOG IS CASE SENSITIVE!  BE SURE TO FOLLOW
THE CASE USED IN THIS EXAMPLE!

//XC4000/XC4000E Example of instantiating BSCAN symbol

module example (a,b,c);

input a, b;

output c;
reg c;


wire tck_net;
wire tdi_net;
wire tms_net;
wire tdo_net;




BSCAN u1 (.TDI(tdi_net), .TMS(tms_net), .TCK(tck_net), .TDO(tdo_net));

TDI u2 (.I(tdi_net));
TMS u3 (.I(tms_net));
TCK u4 (.I(tck_net));

TDO u5 (.O(tdo_net));

always@(posedge b)
	c<=a;


endmodule



Solution 3:

III. Verilog Code for Instantiating BSCAN in the XC5200:


//XC5200 Example of instantiating BSCAN symbol

module example (a,b,c);

input a, b;
output c;

reg c;


wire tck_net, tck_net_in;
wire tdi_net, tdi_net_in;
wire tms_net, tms_net_in;
wire tdo_net, tdo_net_out;




BSCAN u1 (.TDI(tdi_net), .TMS(tms_net), .TCK(tck_net), .TDO(tdo_net));

TDI u2 (.I(tdi_net_in));
TMS u3 (.I(tms_net_in));
TCK u4 (.I(tck_net_in));

TDO u5 (.O(tdo_net_out));

IBUF u6 (.I(tdi_net_in), .O(tdi_net));
IBUF u7 (.I(tms_net_in), .O(tms_net));
IBUF u8 (.I(tck_net_in), .O(tck_net));

OBUF u9 (.I(tdo_net), .O(tdo_net_out));


always@(posedge b)
	c<=a;


endmodule



Solution 4:

IV. Runscript for compiling XC5200 BSCAN Verilog Example:



PART = 5202PC84-5
TOP = example

read -format verilog "bscan5k.v"


set_port_is_pad "*"
insert_pads



set_dont_touch u1
set_dont_touch u2
set_dont_touch u3
set_dont_touch u4
set_dont_touch u5
set_dont_touch u6
set_dont_touch u7
set_dont_touch u8
set_dont_touch u9



compile







set_attribute TOP "part" -type string PART

write -f xnf -h -o "bscan5k.sxnf"



Solution 5:

V. Runscript for compiling XC4000 BSCAN Verilog Example:

PART = 4025ehq240-3
TOP = example

read -format verilog "bscan4k.v"


set_port_is_pad "*"
insert_pads



set_dont_touch u1
set_dont_touch u2
set_dont_touch u3
set_dont_touch u4
set_dont_touch u5

compile





replace_fpga

set_attribute TOP "part" -type string PART

write -f xnf -h -o "bscan4k.sxnf"



Solution 6:

VI. VHDL Code for Instantiating BSCAN in the XC4000:

-- XC4000/XC4000E example of instantiating the BSCAN symbol

entity example is
	port (a, b: in bit; c: out bit);
end example;


architecture xilinx of example is

component bscan
  port(tdi, tms, tck: in bit; tdo: out bit);
end component;

component TCK
  port ( I : out bit );
end component;

component TDI
  port ( I : out bit );
end component;

component TMS
  port ( I : out bit );
end component;

component TDO
  port ( O : in  bit );
end component;



signal tck_net	: bit;
signal tdi_net	: bit;
signal tms_net	: bit;
signal tdo_net	: bit;

begin


u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net, tdo=>tdo_net);

u2: tck port map (i=>tck_net);
u3: tdi port map (i=>tdi_net);
u4: tms port map (i=>tms_net);
u5: tdo port map (o=>tdo_net);

process(b)
begin
if(b'event and b='1') then
 c <= a;
end if;
end process;


end xilinx;



Solution 7:

VII. Runscript for compiling XC4000 BSCAN VHDL Example:



PART = 4025EHQ240-3
TOP  = example

analyze -format vhdl "bscan4k.vhd"
elaborate TOP


set_dont_touch u1
set_dont_touch u2
set_dont_touch u3
set_dont_touch u4
set_dont_touch u5

set_port_is_pad "*"
insert_pads


compile

replace_fpga



set_attribute TOP "part" -type string PART

write -f xnf -h -o "bscan4k.sxnf"



Solution 8:

Note, set_dont_touch/dont_touch are case-sensitive
with respect to instance names.



Solution 9:

VIII. Runscript for compiling XC5200 BSCAN VHDL Example:


PART = 5202PC84-5
TOP = example


analyze -format vhdl "bscan5k.vhd"
elaborate TOP


set_port_is_pad "*"
insert_pads



set_dont_touch u1
set_dont_touch u2
set_dont_touch u3
set_dont_touch u4
set_dont_touch u5
set_dont_touch u6
set_dont_touch u7
set_dont_touch u8
set_dont_touch u9



compile







set_attribute TOP "part" -type string PART

write -f xnf -h -o "bscan5k.sxnf"



End of Record #488