Answers Database

XACT 5.X, Cadence VERILOG-XL: Performing Verilog simulation of Xilinx designs


Record #518

Product Family:  Software

Product Line:  Cadence

Problem Title:
XACT 5.X, Cadence VERILOG-XL: Performing Verilog simulation of Xilinx
designs



Problem Description:
Procedure for doing Verilog timing simulation of Xilinx designs


Solution 1:

To do timing simulation of a Xilinx design in Verilog-XL, you need to have :

1. Cadence Verilog Simulator(Verilog-XL)
2. ES-Verilog (available on XACT 5.2.1 CD), which includes
translators and simulation models to support Verilog
simulation.


 Steps to create a Verilog timing simulation netlist for
 Cadence Verilog  simulator:

 1) Start with a placed and routed LCA file

 2) timenetx design_name 4000  -x   (for a 4000 design.)

     (Use  -x  to skip	XNFBA for Synopsys designs)

     Outputs:  .v,   .sdf  and	.stim (template stimulus file)

 Add your test vectors to the designt.stim template stimulus
 file.

 4) verilog designt.v designt.stim

 Note: designt.v is the Verilog simulation netlist written by
 xnf2verilog, the actual program called by timenetx. Timenetx
 also creates a template file called <design>t.stim in the run
 directory.

      The .stim file has all the I/O signals defined and
randomly asserted.  Users can edit this file to include
additional input patterns, as  well as to define the clock.



End of Record #518