Answers Database

XC4000, SYNOPSYS Design Compiler: Example .synopsys_dc.setup file


Record #534

Product Family:  Software

Product Line:  Synopsys

Problem Title:
XC4000, SYNOPSYS Design Compiler:  Example .synopsys_dc.setup file


Problem Description:
Synopsys Design Compiler: Example of a .synopsys_dc.setup file for the XC4000 fa
mily.


Solution 1:


/* EXAMPLE DESIGN COMPILER STARTUP FILE - .synopsys_dc.setup */
/* FOR XC4000/H/A/D PARTYPES				     */

search_path = { .	\
	<DS401-XACT-Directory>/synopsys/libraries/syn \
	<SYNOPSYS-Directory>/libraries/syn}

link_library = {xprim_4005-5.db xprim_4000-5.db xgen_4000.db \
	xdc_4000-5.db xio_4000-5.db}

target_library = {xprim_4005-5.db xprim_4000-5.db xgen_4000.db \
	xdc_4000-5.db xio_4000-5.db}

symbol_library = xc4000.sdb

define_design_lib WORK -path ./WORK

define_design_lib xblox_4000 -path \
	<DS401-XACT-Directory>/synopsys/libraries/dw/lib/fpga

synthetic_library = {xblox_4000.sldb standard.sldb}

compile_fix_multiple_port_nets = true

bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"
bus_inference_style = "%s<%d>"

edifout_netlist_only = true
edifout_power_and_ground_representation = cell
edifout_write_properties_list = "instance_number port_location part"





End of Record #534