Answers Database
XC3000, SYNOPSYS Design Compiler: Example .synopsys_dc.setup file
Record #537
Product Family: Software
Product Line: Synopsys
Problem Title:
XC3000, SYNOPSYS Design Compiler: Example .synopsys_dc.setup file
Problem Description:
Synopsys Design Compiler (XC3000): Example of a .synopsys_dc.setup file
Solution 1:
SOLUTION:
/* EXAMPLE DESIGN COMPILER STARTUP FILE - .synopsys_dc.setup */
/* For XC3000/A/L and XC3100/A/L PARTYPES */
search_path = {. \
<DS401-XACT-Directory>/synopsys/libraries/syn \
<SYNOPSYS-Directory>/libraries/syn}
link_library = {xprim_3020a-6.db xprim_3000a-6.db \
xgen_3000.db xdc_3000a-6.db}
target_library = {xprim_3020a-6.db xprim_3000a-6.db \
xgen_3000.db xdc_3000a-6.db}
symbol_library = xc3000.sdb
define_design_lib WORK -path ./WORK
compile_fix_multiple_port_nets = true
bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"
bus_inference_style = "%s<%d>"
edifout_netlist_only = true
edifout_power_and_ground_representation = cell
edifout_write_properties_list = "instance_number port_location part"
End of Record #537
For the latest news, design tips, and patch information on the Xilinx design environment, check out the Xilinx Expert Journals! |