Answers Database

SYNOPSYS: How to invert the reset (GSR/GR) pin on the STARTUP block?


Record #549

Product Family:  Software

Product Line:  Synopsys

Problem Title:
SYNOPSYS: How to invert the reset (GSR/GR) pin on the STARTUP block?


Problem Description:
Keywords: GSR, GR, STARTUP, Verilog, VHDL, Synopsys

Urgency: Standard

General Description:

How to acces an active low GSR (global set/reset) for xc4000e/ex/xl or GR
(global reset) for xc5200 on the STARTUP block?

Note: For xc3000 devices, the global reset signal is a dedicated pin on
the device.  Also, all flip-flops and latches reset to 0 after configuration.


Solution 1:

By default, GSR/GR pin are active high.  To change the polarity of these
signals in your VHDL or Verilog code, instantiate an inverter to the net that
sources the GSR/GR pin of the STARTUP block.

The inversion will be absorbed inside the STARTUP block; a function
generator will not be used to generate the inverter.

Since the STARTUP block doesn't have any outputs that are being used in this
example, use the set_dont_touch command so that the compiler doesn't remove
the STARTUP block.

set_dont_touch instance_name

See Xilinx Solution 2370 for reference to GTS in a Verilog design.

See Xilinx Solution 1670 for reference to the outputs (DONEIN, Q1Q4, Q3, Q2)
on the STARTUP block.




Solution 2:

XC4000e/ex/xl -- Verilog code for active low reset

module use_active_low_gsr (reset);

input reset;

wire reset_inv;

INV U0 (.I (reset), .O (reset_inv));
// the signal reset_inv initializes all registers using the
// global STARTUP signal
STARTUP U1 (.GSR (reset_inv));

endmodule


XC4000e/ex/xl -- Run-script for compiling STARTUP Verilog Example:

PART = 4003epc84-1
TOP = use_active_low_gsr

read -format verilog TOP + ".v"

set_port_is_pad "*"
insert_pads

set_dont_touch U1

compile

replace_fpga

set_attribute TOP "part" -type string PART

write -format xnf -hierarchy -output TOP + ".sxnf"



Solution 3:

XC4000e/ex/xl -- VHDL code for active low reset

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity use_active_low_gsr is
      port (reset : in STD_LOGIC);
end use_active_low_gsr;

architecture xilinx of use_active_low_gsr is

component INV
      port(I : in STD_LOGIC;
	   O : out STD_LOGIC);
end component;

component STARTUP
      port(GSR : in STD_LOGIC);
end component;

signal reset_inv : STD_LOGIC;

begin

    U0: INV port map (I => reset,
		      O => reset_inv);
-- the signal reset_inv initializes all registers using the
-- global STARTUP signal
    U1: STARTUP port map (GSR => reset_inv);

end xilinx;


XC4000e/ex/xl -- Run-script for compiling STARTUP VHDL Example:

PART = 4003epc84-1
TOP = use_active_low_gsr

analyze -format vhdl TOP + ".vhd"
elaborate TOP

set_port_is_pad "*"
insert_pads

set_dont_touch U1

compile

replace_fpga

set_attribute TOP "part" -type string PART

write -format xnf -hierarchy -output TOP + ".sxnf"




Solution 4:

XC5200 -- Verilog code for active low reset

module use_active_low_gr (reset);

input reset;

wire reset_inv;

INV U0 (.I (reset), .O (reset_inv));
// the signal reset_inv initializes all registers using the
// global STARTUP signal
STARTUP U1 (.GR (reset_inv));

endmodule


XC5200 -- Run-script for compiling STARTUP Verilog Example:

PART = 5202pc84-3
TOP = use_active_low_gr

read -format verilog TOP + ".v"

set_port_is_pad "*"
insert_pads

set_dont_touch U1

compile

set_attribute TOP "part" -type string PART

write -format xnf -hierarchy -output TOP + ".sxnf"




Solution 5:

XC5200 -- VHDL code for active low reset

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity use_active_low_gr is
      port (reset : in STD_LOGIC);
end use_active_low_gr;

architecture xilinx of use_active_low_gr is

component INV
      port(I : in STD_LOGIC;
	   O : out STD_LOGIC);
end component;

component STARTUP
      port(GR : in STD_LOGIC);
end component;

signal reset_inv : STD_LOGIC;

begin

    U0: INV port map (I => reset,
		      O => reset_inv);
-- the signal reset_inv initializes all registers using the
-- global STARTUP signal
    U1: STARTUP port map (GR => reset_inv);

end xilinx;


XC5200 -- Run-script for compiling STARTUP VHDL Example:

PART = 5202pc84-3
TOP = use_active_low_gr

analyze -format vhdl TOP + ".vhd"
elaborate TOP

set_port_is_pad "*"
insert_pads

set_dont_touch U1

compile

set_attribute TOP "part" -type string PART

write -format xnf -hierarchy -output TOP + ".sxnf"



End of Record #549